/netbsd-src/sys/external/bsd/drm2/dist/drm/radeon/ |
H A D | radeon_rv740_dpm.c | 99 u32 rv740_get_dll_speed(bool is_gddr5, u32 memory_clock) in rv740_get_dll_speed() argument 110 data_rate = (u16)(memory_clock * factor / 1000); in rv740_get_dll_speed() 192 u32 engine_clock, u32 memory_clock, in rv740_populate_mclk_value() argument 210 memory_clock, false, ÷rs); in rv740_populate_mclk_value() 252 u32 vco_freq = memory_clock * dividers.post_div; in rv740_populate_mclk_value() 271 memory_clock); in rv740_populate_mclk_value() 276 mclk->mclk770.mclk_value = cpu_to_be32(memory_clock); in rv740_populate_mclk_value() 410 u8 rv740_get_mclk_frequency_ratio(u32 memory_clock) in rv740_get_mclk_frequency_ratio() argument 414 if ((memory_clock < 10000) || (memory_clock > 47500)) in rv740_get_mclk_frequency_ratio() 417 mc_para_index = (u8)((memory_clock - 10000) / 2500); in rv740_get_mclk_frequency_ratio()
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H A D | rv770_dpm.h | 186 u32 engine_clock, u32 memory_clock, 207 u32 engine_clock, u32 memory_clock, 214 u8 rv740_get_mclk_frequency_ratio(u32 memory_clock); 215 u32 rv740_get_dll_speed(bool is_gddr5, u32 memory_clock);
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H A D | radeon_cypress_dpm.c | 480 u32 engine_clock, u32 memory_clock, in cypress_populate_mclk_value() argument 507 memory_clock, strobe_mode, ÷rs); in cypress_populate_mclk_value() 561 u32 vco_freq = memory_clock * dividers.post_div; in cypress_populate_mclk_value() 580 memory_clock); in cypress_populate_mclk_value() 603 mclk->mclk770.mclk_value = cpu_to_be32(memory_clock); in cypress_populate_mclk_value() 617 u32 memory_clock, bool strobe_mode) in cypress_get_mclk_frequency_ratio() argument 623 if (memory_clock < 10000) in cypress_get_mclk_frequency_ratio() 625 else if (memory_clock > 47500) in cypress_get_mclk_frequency_ratio() 628 mc_para_index = (u8)((memory_clock - 10000) / 2500); in cypress_get_mclk_frequency_ratio() 630 if (memory_clock < 65000) in cypress_get_mclk_frequency_ratio() [all …]
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H A D | cypress_dpm.h | 127 u32 engine_clock, u32 memory_clock); 159 u32 memory_clock, bool strobe_mode);
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H A D | radeon_rv730_dpm.c | 124 u32 engine_clock, u32 memory_clock, in rv730_populate_mclk_value() argument 140 memory_clock, false, ÷rs); in rv730_populate_mclk_value() 172 u32 vco_freq = memory_clock * post_divider; in rv730_populate_mclk_value() 192 mclk->mclk730.mclk_value = cpu_to_be32(memory_clock); in rv730_populate_mclk_value()
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H A D | radeon_ci_dpm.c | 174 extern u8 si_get_ddr3_mclk_frequency_ratio(u32 memory_clock); 175 extern u8 si_get_mclk_frequency_ratio(u32 memory_clock, bool strobe_mode); 2503 const u32 memory_clock, in ci_register_patching_mc_arb() argument 2515 if ((memory_clock > 100000) && (memory_clock <= 125000)) { in ci_register_patching_mc_arb() 2519 } else if ((memory_clock > 125000) && (memory_clock <= 137500)) { in ci_register_patching_mc_arb() 2795 u32 memory_clock, in ci_calculate_mclk_params() argument 2813 ret = radeon_atom_get_memory_pll_dividers(rdev, memory_clock, strobe_mode, &mpll_param); in ci_calculate_mclk_params() 2840 freq_nom = memory_clock * 4 * (1 << mpll_param.post_div); in ci_calculate_mclk_params() 2842 freq_nom = memory_clock * 2 * (1 << mpll_param.post_div); in ci_calculate_mclk_params() 2867 mclk->MclkFrequency = memory_clock; in ci_calculate_mclk_params() [all …]
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H A D | radeon_rv770_dpm.c | 322 static void rv770_calculate_fractional_mpll_feedback_divider(u32 memory_clock, in rv770_calculate_fractional_mpll_feedback_divider() argument 333 fyclk = (memory_clock * 8) / 2; in rv770_calculate_fractional_mpll_feedback_divider() 335 fyclk = (memory_clock * 4) / 2; in rv770_calculate_fractional_mpll_feedback_divider() 391 u32 engine_clock, u32 memory_clock, in rv770_populate_mclk_value() argument 415 memory_clock, false, ÷rs); in rv770_populate_mclk_value() 422 rv770_calculate_fractional_mpll_feedback_divider(memory_clock, reference_clock, in rv770_populate_mclk_value() 449 rv770_calculate_fractional_mpll_feedback_divider(memory_clock, in rv770_populate_mclk_value() 477 mclk->mclk770.mclk_value = cpu_to_be32(memory_clock); in rv770_populate_mclk_value()
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H A D | radeon_si_dpm.c | 3828 u8 si_get_ddr3_mclk_frequency_ratio(u32 memory_clock) in si_get_ddr3_mclk_frequency_ratio() argument 3832 if (memory_clock < 10000) in si_get_ddr3_mclk_frequency_ratio() 3834 else if (memory_clock >= 80000) in si_get_ddr3_mclk_frequency_ratio() 3837 mc_para_index = (u8)((memory_clock - 10000) / 5000 + 1); in si_get_ddr3_mclk_frequency_ratio() 3841 u8 si_get_mclk_frequency_ratio(u32 memory_clock, bool strobe_mode) in si_get_mclk_frequency_ratio() argument 3846 if (memory_clock < 12500) in si_get_mclk_frequency_ratio() 3848 else if (memory_clock > 47500) in si_get_mclk_frequency_ratio() 3851 mc_para_index = (u8)((memory_clock - 10000) / 2500); in si_get_mclk_frequency_ratio() 3853 if (memory_clock < 65000) in si_get_mclk_frequency_ratio() 3855 else if (memory_clock > 135000) in si_get_mclk_frequency_ratio() [all …]
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H A D | radeon_ni_dpm.c | 2166 u32 memory_clock, in ni_populate_mclk_value() argument 2188 memory_clock, strobe_mode, ÷rs); in ni_populate_mclk_value() 2242 u32 vco_freq = memory_clock * dividers.post_div; in ni_populate_mclk_value() 2261 memory_clock); in ni_populate_mclk_value() 2285 mclk->mclk_value = cpu_to_be32(memory_clock); in ni_populate_mclk_value()
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/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/powerplay/smumgr/ |
H A D | amdgpu_iceland_smumgr.c | 1051 uint32_t memory_clock, in iceland_calculate_mclk_params() argument 1073 memory_clock, &mpll_param, strobe_mode); in iceland_calculate_mclk_params() 1124 freq_nom = memory_clock * 4 * (1 << mpll_param.mpll_post_divider); in iceland_calculate_mclk_params() 1126 freq_nom = memory_clock * 2 * (1 << mpll_param.mpll_post_divider); in iceland_calculate_mclk_params() 1160 mclk->MclkFrequency = memory_clock; in iceland_calculate_mclk_params() 1174 static uint8_t iceland_get_mclk_frequency_ratio(uint32_t memory_clock, in iceland_get_mclk_frequency_ratio() argument 1180 if (memory_clock < 12500) { in iceland_get_mclk_frequency_ratio() 1182 } else if (memory_clock > 47500) { in iceland_get_mclk_frequency_ratio() 1185 mc_para_index = (uint8_t)((memory_clock - 10000) / 2500); in iceland_get_mclk_frequency_ratio() 1188 if (memory_clock < 65000) { in iceland_get_mclk_frequency_ratio() [all …]
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H A D | amdgpu_ci_smumgr.c | 1028 uint32_t memory_clock, in ci_calculate_mclk_params() argument 1049 memory_clock, &mpll_param, strobe_mode); in ci_calculate_mclk_params() 1081 freq_nom = memory_clock * 4 * (1 << mpll_param.mpll_post_divider); in ci_calculate_mclk_params() 1083 freq_nom = memory_clock * 2 * (1 << mpll_param.mpll_post_divider); in ci_calculate_mclk_params() 1108 mclk->MclkFrequency = memory_clock; in ci_calculate_mclk_params() 1122 static uint8_t ci_get_mclk_frequency_ratio(uint32_t memory_clock, in ci_get_mclk_frequency_ratio() argument 1128 if (memory_clock < 12500) in ci_get_mclk_frequency_ratio() 1130 else if (memory_clock > 47500) in ci_get_mclk_frequency_ratio() 1133 mc_para_index = (uint8_t)((memory_clock - 10000) / 2500); in ci_get_mclk_frequency_ratio() 1135 if (memory_clock < 65000) in ci_get_mclk_frequency_ratio() [all …]
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H A D | amdgpu_tonga_smumgr.c | 794 uint32_t memory_clock, in tonga_calculate_mclk_params() argument 816 memory_clock, &mpll_param, strobe_mode); in tonga_calculate_mclk_params() 876 freq_nom = memory_clock * 4 * (1 << mpll_param.mpll_post_divider); in tonga_calculate_mclk_params() 878 freq_nom = memory_clock * 2 * (1 << mpll_param.mpll_post_divider); in tonga_calculate_mclk_params() 911 mclk->MclkFrequency = memory_clock; in tonga_calculate_mclk_params() 925 static uint8_t tonga_get_mclk_frequency_ratio(uint32_t memory_clock, in tonga_get_mclk_frequency_ratio() argument 931 if (memory_clock < 12500) in tonga_get_mclk_frequency_ratio() 933 else if (memory_clock > 47500) in tonga_get_mclk_frequency_ratio() 936 mc_para_index = (uint8_t)((memory_clock - 10000) / 2500); in tonga_get_mclk_frequency_ratio() 938 if (memory_clock < 65000) in tonga_get_mclk_frequency_ratio() [all …]
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/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/powerplay/hwmgr/ |
H A D | ppatomctrl.h | 296 …t_memory_clock_spread_spectrum(struct pp_hwmgr *hwmgr, const uint32_t memory_clock, pp_atomctrl_in… 299 …et_engine_dram_timings_rv770(struct pp_hwmgr *hwmgr, uint32_t engine_clock, uint32_t memory_clock); 318 extern int atomctrl_set_ac_timing_ai(struct pp_hwmgr *hwmgr, uint32_t memory_clock,
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H A D | amdgpu_smu7_hwmgr.c | 2924 if (smu7_ps->performance_levels[i].memory_clock > max_limits->mclk) in smu7_apply_state_adjust_rules() 2925 smu7_ps->performance_levels[i].memory_clock = max_limits->mclk; in smu7_apply_state_adjust_rules() 2972 mclk = smu7_ps->performance_levels[0].memory_clock; in smu7_apply_state_adjust_rules() 2976 [smu7_ps->performance_level_count - 1].memory_clock; in smu7_apply_state_adjust_rules() 2987 smu7_ps->performance_levels[0].memory_clock = mclk; in smu7_apply_state_adjust_rules() 2996 if (mclk < smu7_ps->performance_levels[1].memory_clock) in smu7_apply_state_adjust_rules() 2997 mclk = smu7_ps->performance_levels[1].memory_clock; in smu7_apply_state_adjust_rules() 2999 smu7_ps->performance_levels[0].memory_clock = mclk; in smu7_apply_state_adjust_rules() 3000 smu7_ps->performance_levels[1].memory_clock = mclk; in smu7_apply_state_adjust_rules() 3002 if (smu7_ps->performance_levels[1].memory_clock < in smu7_apply_state_adjust_rules() [all …]
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H A D | amdgpu_ppatomctrl.c | 180 uint32_t memory_clock) in atomctrl_set_engine_dram_timings_rv770() argument 193 cpu_to_le32(memory_clock & SET_CLOCK_FREQ_MASK); in atomctrl_set_engine_dram_timings_rv770() 1284 const uint32_t memory_clock, in atomctrl_get_memory_clock_spread_spectrum() argument 1288 ASIC_INTERNAL_MEMORY_SS, memory_clock, ssInfo); in atomctrl_get_memory_clock_spread_spectrum() 1323 int atomctrl_set_ac_timing_ai(struct pp_hwmgr *hwmgr, uint32_t memory_clock, in atomctrl_set_ac_timing_ai() argument 1331 memory_clock & SET_CLOCK_FREQ_MASK; in atomctrl_set_ac_timing_ai()
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H A D | amdgpu_hardwaremanager.c | 399 pclock_info->min_mem_clk = performance_level.memory_clock; in phm_get_clock_info() 409 pclock_info->max_mem_clk = performance_level.memory_clock; in phm_get_clock_info()
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H A D | smu7_hwmgr.h | 57 uint32_t memory_clock; member
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H A D | amdgpu_smu10_hwmgr.c | 949 level->memory_clock = data->clock_vol_info.vdd_dep_on_fclk->entries[0].clk; in smu10_get_performance_level() 952 level->memory_clock = data->clock_vol_info.vdd_dep_on_fclk->entries[ in smu10_get_performance_level()
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H A D | amdgpu_smu8_hwmgr.c | 1586 level->memory_clock = data->sys_info.nbp_memory_clock[SMU8_NUM_NBPMEMORYCLOCK - 1]; in smu8_get_performance_level() 1588 level->memory_clock = data->sys_info.nbp_memory_clock[0]; in smu8_get_performance_level()
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/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/powerplay/inc/ |
H A D | amdgpu_smu.h | 195 uint32_t memory_clock; member 320 uint32_t memory_clock; member
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H A D | hardwaremanager.h | 275 uint32_t memory_clock; member
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/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/ |
H A D | amdgpu_si_dpm.c | 4295 static u8 si_get_ddr3_mclk_frequency_ratio(u32 memory_clock) in si_get_ddr3_mclk_frequency_ratio() argument 4299 if (memory_clock < 10000) in si_get_ddr3_mclk_frequency_ratio() 4301 else if (memory_clock >= 80000) in si_get_ddr3_mclk_frequency_ratio() 4304 mc_para_index = (u8)((memory_clock - 10000) / 5000 + 1); in si_get_ddr3_mclk_frequency_ratio() 4308 static u8 si_get_mclk_frequency_ratio(u32 memory_clock, bool strobe_mode) in si_get_mclk_frequency_ratio() argument 4313 if (memory_clock < 12500) in si_get_mclk_frequency_ratio() 4315 else if (memory_clock > 47500) in si_get_mclk_frequency_ratio() 4318 mc_para_index = (u8)((memory_clock - 10000) / 2500); in si_get_mclk_frequency_ratio() 4320 if (memory_clock < 65000) in si_get_mclk_frequency_ratio() 4322 else if (memory_clock > 135000) in si_get_mclk_frequency_ratio() [all …]
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/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/powerplay/ |
H A D | amdgpu_smu.c | 1596 clk_info->min_mem_clk = level.memory_clock; in smu_get_clock_info() 1604 clk_info->min_mem_clk = level.memory_clock; in smu_get_clock_info()
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H A D | amdgpu_navi10_ppt.c | 1466 min_clocks.memory_clock = smu->display_config->min_mem_set_clock; in navi10_notify_smc_display_config() 1489 ret = smu_set_hard_freq_range(smu, SMU_UCLK, min_clocks.memory_clock/100, 0); in navi10_notify_smc_display_config()
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H A D | amdgpu_vega20_ppt.c | 2248 min_clocks.memory_clock = smu->display_config->min_mem_set_clock; in vega20_notify_smc_display_config() 2269 memtable->dpm_state.hard_min_level = min_clocks.memory_clock/100; in vega20_notify_smc_display_config()
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