Home
last modified time | relevance | path

Searched refs:mclk_table (Results 1 – 16 of 16) sorted by relevance

/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/powerplay/hwmgr/
H A Damdgpu_smu7_hwmgr.c647 &data->dpm_table.mclk_table, in smu7_reset_dpm_tables()
715 data->dpm_table.mclk_table.count = 0; in smu7_setup_dpm_tables_v0()
717 if (i == 0 || data->dpm_table.mclk_table.dpm_levels[data->dpm_table.mclk_table.count-1].value != in smu7_setup_dpm_tables_v0()
719 data->dpm_table.mclk_table.dpm_levels[data->dpm_table.mclk_table.count].value = in smu7_setup_dpm_tables_v0()
721 …data->dpm_table.mclk_table.dpm_levels[data->dpm_table.mclk_table.count].enabled = (i == 0) ? 1 : 0; in smu7_setup_dpm_tables_v0()
722 data->dpm_table.mclk_table.count++; in smu7_setup_dpm_tables_v0()
810 data->dpm_table.mclk_table.count = 0; in smu7_setup_dpm_tables_v1()
812 if (i == 0 || data->dpm_table.mclk_table.dpm_levels in smu7_setup_dpm_tables_v1()
813 [data->dpm_table.mclk_table.count - 1].value != in smu7_setup_dpm_tables_v1()
815 data->dpm_table.mclk_table.dpm_levels[data->dpm_table.mclk_table.count].value = in smu7_setup_dpm_tables_v1()
[all …]
H A Damdgpu_smu10_hwmgr.c841 struct smu10_voltage_dependency_table *mclk_table = in smu10_force_clock_level() local
869 if (low > mclk_table->count - 1 || high > mclk_table->count - 1) in smu10_force_clock_level()
874 mclk_table->entries[low].clk/100); in smu10_force_clock_level()
878 mclk_table->entries[high].clk/100); in smu10_force_clock_level()
892 struct smu10_voltage_dependency_table *mclk_table = in smu10_print_clock_levels() local
923 for (i = 0; i < mclk_table->count; i++) in smu10_print_clock_levels()
926 mclk_table->entries[i].clk / 100, in smu10_print_clock_levels()
927 ((mclk_table->entries[i].clk / 100) in smu10_print_clock_levels()
H A Damdgpu_vega10_processpptables.c614 phm_ppt_v1_clock_voltage_dependency_table *mclk_table; in get_mclk_voltage_dependency_table() local
623 mclk_table = kzalloc(table_size, GFP_KERNEL); in get_mclk_voltage_dependency_table()
625 if (!mclk_table) in get_mclk_voltage_dependency_table()
628 mclk_table->count = (uint32_t)mclk_dep_table->ucNumEntries; in get_mclk_voltage_dependency_table()
631 mclk_table->entries[i].vddInd = in get_mclk_voltage_dependency_table()
633 mclk_table->entries[i].vddciInd = in get_mclk_voltage_dependency_table()
635 mclk_table->entries[i].mvddInd = in get_mclk_voltage_dependency_table()
637 mclk_table->entries[i].clk = in get_mclk_voltage_dependency_table()
641 *pp_vega10_mclk_dep_table = mclk_table; in get_mclk_voltage_dependency_table()
H A Damdgpu_vega10_hwmgr.c674 struct phm_ppt_v1_clock_voltage_dependency_table *mclk_table = in vega10_patch_voltage_dependency_tables_with_lookup_table() local
701 for (entry_id = 0; entry_id < mclk_table->count; ++entry_id) { in vega10_patch_voltage_dependency_tables_with_lookup_table()
702 voltage_id = mclk_table->entries[entry_id].vddInd; in vega10_patch_voltage_dependency_tables_with_lookup_table()
703 mclk_table->entries[entry_id].vddc = in vega10_patch_voltage_dependency_tables_with_lookup_table()
705 voltage_id = mclk_table->entries[entry_id].vddciInd; in vega10_patch_voltage_dependency_tables_with_lookup_table()
706 mclk_table->entries[entry_id].vddci = in vega10_patch_voltage_dependency_tables_with_lookup_table()
708 voltage_id = mclk_table->entries[entry_id].mvddInd; in vega10_patch_voltage_dependency_tables_with_lookup_table()
709 mclk_table->entries[entry_id].mvdd = in vega10_patch_voltage_dependency_tables_with_lookup_table()
3332 struct vega10_single_dpm_table *mclk_table = &(data->dpm_table.mem_table); in vega10_find_dpm_states_clocks_in_dpm_table() local
3349 for (i = 0; i < mclk_table->count; i++) { in vega10_find_dpm_states_clocks_in_dpm_table()
[all …]
H A Damdgpu_process_pptables_v1_0.c379 phm_ppt_v1_clock_voltage_dependency_table *mclk_table; in get_mclk_voltage_dependency_table() local
389 mclk_table = kzalloc(table_size, GFP_KERNEL); in get_mclk_voltage_dependency_table()
391 if (NULL == mclk_table) in get_mclk_voltage_dependency_table()
394 mclk_table->count = (uint32_t)mclk_dep_table->ucNumEntries; in get_mclk_voltage_dependency_table()
399 entries, mclk_table, i); in get_mclk_voltage_dependency_table()
410 *pp_tonga_mclk_dep_table = mclk_table; in get_mclk_voltage_dependency_table()
H A Dsmu7_hwmgr.h107 struct smu7_single_dpm_table mclk_table; member
H A Damdgpu_vega12_hwmgr.c2537 struct vega12_single_dpm_table *mclk_table = &(data->dpm_table.mem_table);
2540 int value = mclk_table->dpm_levels[mclk_table->count - 1].value;
H A Damdgpu_vega20_hwmgr.c1498 struct vega20_single_dpm_table *mclk_table = in vega20_get_mclk_od() local
1502 int value = mclk_table->dpm_levels[mclk_table->count - 1].value; in vega20_get_mclk_od()
/netbsd-src/sys/external/bsd/drm2/dist/drm/radeon/
H A Dradeon_ci_dpm.c2562 for (j = 0; j < pi->dpm_table.mclk_table.count; j++) { in ci_do_program_memory_timing_parameters()
2565 pi->dpm_table.mclk_table.dpm_levels[j].value, in ci_do_program_memory_timing_parameters()
3342 for (i = 0; i < dpm_table->mclk_table.count; i++) { in ci_populate_all_memory_levels()
3343 if (dpm_table->mclk_table.dpm_levels[i].value == 0) in ci_populate_all_memory_levels()
3346 dpm_table->mclk_table.dpm_levels[i].value, in ci_populate_all_memory_levels()
3354 if ((dpm_table->mclk_table.count >= 2) && in ci_populate_all_memory_levels()
3364 pi->smc_state_table.MemoryDpmLevelCount = (u8)dpm_table->mclk_table.count; in ci_populate_all_memory_levels()
3366 ci_get_dpm_level_enable_mask_value(&dpm_table->mclk_table); in ci_populate_all_memory_levels()
3368 pi->smc_state_table.MemoryLevel[dpm_table->mclk_table.count - 1].DisplayWatermark = in ci_populate_all_memory_levels()
3473 &pi->dpm_table.mclk_table, in ci_setup_default_dpm_tables()
[all …]
H A Dci_dpm.h72 struct ci_single_dpm_table mclk_table; member
/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/powerplay/smumgr/
H A Damdgpu_iceland_smumgr.c1366 for (i = 0; i < dpm_table->mclk_table.count; i++) { in iceland_populate_all_memory_levels()
1367 PP_ASSERT_WITH_CODE((0 != dpm_table->mclk_table.dpm_levels[i].value), in iceland_populate_all_memory_levels()
1369 result = iceland_populate_single_memory_level(hwmgr, dpm_table->mclk_table.dpm_levels[i].value, in iceland_populate_all_memory_levels()
1387 smu_data->smc_state_table.MemoryDpmLevelCount = (uint8_t)dpm_table->mclk_table.count; in iceland_populate_all_memory_levels()
1388 …vel_enable_mask.mclk_dpm_enable_mask = phm_get_dpm_level_enable_mask_value(&dpm_table->mclk_table); in iceland_populate_all_memory_levels()
1390 …smu_data->smc_state_table.MemoryLevel[dpm_table->mclk_table.count-1].DisplayWatermark = PPSMC_DISP… in iceland_populate_all_memory_levels()
1627 for (j = 0; j < data->dpm_table.mclk_table.count; j++) { in iceland_program_memory_timing_parameters()
1630 data->dpm_table.mclk_table.dpm_levels[j].value, in iceland_program_memory_timing_parameters()
1672 result = phm_find_boot_level(&(data->dpm_table.mclk_table), in iceland_populate_smc_boot_level()
1766 for (i = 0; i < data->dpm_table.mclk_table.count; i++) { in iceland_convert_mc_reg_table_to_smc()
[all …]
H A Damdgpu_vegam_smumgr.c1051 for (i = 0; i < dpm_table->mclk_table.count; i++) { in vegam_populate_all_memory_levels()
1052 PP_ASSERT_WITH_CODE((0 != dpm_table->mclk_table.dpm_levels[i].value), in vegam_populate_all_memory_levels()
1056 dpm_table->mclk_table.dpm_levels[i].value, in vegam_populate_all_memory_levels()
1069 (uint8_t)dpm_table->mclk_table.count; in vegam_populate_all_memory_levels()
1071 phm_get_dpm_level_enable_mask_value(&dpm_table->mclk_table); in vegam_populate_all_memory_levels()
1073 for (i = 0; i < dpm_table->mclk_table.count; i++) in vegam_populate_all_memory_levels()
1077 levels[dpm_table->mclk_table.count - 1].DisplayWatermark = in vegam_populate_all_memory_levels()
1290 for (j = 0; j < hw_data->dpm_table.mclk_table.count; j++) { in vegam_program_memory_timing_parameters()
1293 hw_data->dpm_table.mclk_table.dpm_levels[j].value, in vegam_program_memory_timing_parameters()
1382 result = phm_find_boot_level(&(data->dpm_table.mclk_table), in vegam_populate_smc_boot_level()
H A Damdgpu_fiji_smumgr.c1241 for (i = 0; i < dpm_table->mclk_table.count; i++) { in fiji_populate_all_memory_levels()
1242 PP_ASSERT_WITH_CODE((0 != dpm_table->mclk_table.dpm_levels[i].value), in fiji_populate_all_memory_levels()
1246 dpm_table->mclk_table.dpm_levels[i].value, in fiji_populate_all_memory_levels()
1264 (uint8_t)dpm_table->mclk_table.count; in fiji_populate_all_memory_levels()
1266 phm_get_dpm_level_enable_mask_value(&dpm_table->mclk_table); in fiji_populate_all_memory_levels()
1268 levels[dpm_table->mclk_table.count - 1].DisplayWatermark = in fiji_populate_all_memory_levels()
1381 data->dpm_table.mclk_table.dpm_levels[0].value; in fiji_populate_smc_acpi_level()
1402 data->dpm_table.mclk_table.dpm_levels[0].value, in fiji_populate_smc_acpi_level()
1540 for (j = 0; j < data->dpm_table.mclk_table.count; j++) { in fiji_program_memory_timing_parameters()
1543 data->dpm_table.mclk_table.dpm_levels[j].value, in fiji_program_memory_timing_parameters()
[all …]
H A Damdgpu_ci_smumgr.c1319 for (i = 0; i < dpm_table->mclk_table.count; i++) { in ci_populate_all_memory_levels()
1320 PP_ASSERT_WITH_CODE((0 != dpm_table->mclk_table.dpm_levels[i].value), in ci_populate_all_memory_levels()
1322 result = ci_populate_single_memory_level(hwmgr, dpm_table->mclk_table.dpm_levels[i].value, in ci_populate_all_memory_levels()
1332 if ((dpm_table->mclk_table.count >= 2) in ci_populate_all_memory_levels()
1342 smu_data->smc_state_table.MemoryDpmLevelCount = (uint8_t)dpm_table->mclk_table.count; in ci_populate_all_memory_levels()
1343 …vel_enable_mask.mclk_dpm_enable_mask = phm_get_dpm_level_enable_mask_value(&dpm_table->mclk_table); in ci_populate_all_memory_levels()
1344 …smu_data->smc_state_table.MemoryLevel[dpm_table->mclk_table.count-1].DisplayWatermark = PPSMC_DISP… in ci_populate_all_memory_levels()
1664 for (j = 0; j < data->dpm_table.mclk_table.count; j++) { in ci_program_memory_timing_parameters()
1667 data->dpm_table.mclk_table.dpm_levels[j].value, in ci_program_memory_timing_parameters()
1709 result = phm_find_boot_level(&(data->dpm_table.mclk_table), in ci_populate_smc_boot_level()
[all …]
H A Damdgpu_polaris10_smumgr.c1144 for (i = 0; i < dpm_table->mclk_table.count; i++) { in polaris10_populate_all_memory_levels()
1145 PP_ASSERT_WITH_CODE((0 != dpm_table->mclk_table.dpm_levels[i].value), in polaris10_populate_all_memory_levels()
1149 dpm_table->mclk_table.dpm_levels[i].value, in polaris10_populate_all_memory_levels()
1151 if (i == dpm_table->mclk_table.count - 1) { in polaris10_populate_all_memory_levels()
1168 (uint8_t)dpm_table->mclk_table.count; in polaris10_populate_all_memory_levels()
1170 phm_get_dpm_level_enable_mask_value(&dpm_table->mclk_table); in polaris10_populate_all_memory_levels()
1267 data->dpm_table.mclk_table.dpm_levels[0].value, in polaris10_populate_smc_acpi_level()
1376 for (j = 0; j < hw_data->dpm_table.mclk_table.count; j++) { in polaris10_program_memory_timing_parameters()
1379 hw_data->dpm_table.mclk_table.dpm_levels[j].value, in polaris10_program_memory_timing_parameters()
1382 result = atomctrl_set_ac_timing_ai(hwmgr, hw_data->dpm_table.mclk_table.dpm_levels[j].value, j); in polaris10_program_memory_timing_parameters()
[all …]
H A Damdgpu_tonga_smumgr.c1112 for (i = 0; i < dpm_table->mclk_table.count; i++) { in tonga_populate_all_memory_levels()
1113 PP_ASSERT_WITH_CODE((0 != dpm_table->mclk_table.dpm_levels[i].value), in tonga_populate_all_memory_levels()
1118 dpm_table->mclk_table.dpm_levels[i].value, in tonga_populate_all_memory_levels()
1135 smu_data->smc_state_table.MemoryDpmLevelCount = (uint8_t)dpm_table->mclk_table.count; in tonga_populate_all_memory_levels()
1136 …vel_enable_mask.mclk_dpm_enable_mask = phm_get_dpm_level_enable_mask_value(&dpm_table->mclk_table); in tonga_populate_all_memory_levels()
1138 …smu_data->smc_state_table.MemoryLevel[dpm_table->mclk_table.count-1].DisplayWatermark = PPSMC_DISP… in tonga_populate_all_memory_levels()
1503 for (j = 0; j < data->dpm_table.mclk_table.count; j++) { in tonga_program_memory_timing_parameters()
1506 data->dpm_table.mclk_table.dpm_levels[j].value, in tonga_program_memory_timing_parameters()
1550 result = phm_find_boot_level(&(data->dpm_table.mclk_table), in tonga_populate_smc_boot_level()
2145 for (i = 0; i < data->dpm_table.mclk_table.count; i++) { in tonga_convert_mc_reg_table_to_smc()
[all …]