Searched refs:link_width (Results 1 – 6 of 6) sorted by relevance
322 sc->link_width = (lnk >> 4) & 0x3f; in cxgb_controller_attach()329 if (sc->link_width != 0 && sc->link_width <= 4 && in cxgb_controller_attach()333 sc->link_width); in cxgb_controller_attach()
322 uint32_t link_width; member
156 uint16_t link_width; /* PCIe link width */ member
475 aprint_normal_dev(dev, "PCIe x%d ", sc->link_width); in bnx_print_adapter_info() 545 sc->link_width = (link_status & PCIE_LCSR_NLW) >> 20; in bnx_probe_pci_caps()
169 uint32_t link_width; in smu7_get_current_pcie_lane_number() local172 link_width = PHM_READ_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__PCIE, in smu7_get_current_pcie_lane_number()175 PP_ASSERT_WITH_CODE((7 >= link_width), in smu7_get_current_pcie_lane_number()178 return decode_pcie_lane_width(link_width); in smu7_get_current_pcie_lane_number()
4831 u32 link_width = 0; in ci_get_current_pcie_lane_number() local4833 link_width = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL) & LC_LINK_WIDTH_RD_MASK; in ci_get_current_pcie_lane_number()4834 link_width >>= LC_LINK_WIDTH_RD_SHIFT; in ci_get_current_pcie_lane_number()4836 switch (link_width) { in ci_get_current_pcie_lane_number()