| /netbsd-src/crypto/external/bsd/heimdal/dist/lib/hx509/ |
| H A D | test_ca.in | 58 ${hxtool} issue-certificate \
106 ${hxtool} issue-certificate \
114 ${hxtool} issue-certificate \
123 ${hxtool} issue-certificate \
132 ${hxtool} issue-certificate \
141 ${hxtool} issue-certificate \
169 ${hxtool} issue-certificate \
189 ${hxtool} issue-certificate \
198 ${hxtool} issue-certificate \
206 ${hxtool} issue-certificate \
[all …]
|
| H A D | test_windows.in | 52 ${hxtool} issue-certificate \
54 --issue-ca \
61 ${hxtool} issue-certificate \
74 ${hxtool} issue-certificate \
|
| /netbsd-src/external/gpl3/gcc.old/dist/gcc/config/arc/ |
| H A D | arc700.md | 29 (define_cpu_unit "core, dmp, write_port, dmp_write_port, multiplier, issue, blockage, simd_unit" "…
35 "issue+core, issue+core+write_port, write_port")
40 "issue+blockage, blockage*2, write_port")
45 "issue+dmp_write_port+blockage, blockage*9")
50 "issue+core, nothing, write_port")
55 "issue+core, nothing, write_port")
60 "issue+core, nothing, write_port")
65 "issue+core, nothing, write_port")
70 "issue+core, nothing, write_port")
75 "issue+core, nothing, write_port")
[all …]
|
| /netbsd-src/external/gpl3/gcc/dist/gcc/config/arc/ |
| H A D | arc700.md | 29 (define_cpu_unit "core, dmp, write_port, dmp_write_port, multiplier, issue, blockage, simd_unit" "…
35 "issue+core, issue+core+write_port, write_port")
40 "issue+blockage, blockage*2, write_port")
45 "issue+dmp_write_port+blockage, blockage*9")
50 "issue+core, nothing, write_port")
55 "issue+core, nothing, write_port")
60 "issue+core, nothing, write_port")
65 "issue+core, nothing, write_port")
70 "issue+core, nothing, write_port")
75 "issue+core, nothing, write_port")
[all …]
|
| /netbsd-src/external/gpl3/gcc/dist/gcc/config/epiphany/ |
| H A D | epiphany-sched.md | 27 ;; Since epiphany is a dual issue machine, it is as if there are two
42 ;; This reservation is to simplify the dual issue description.
44 (define_reservation "issue" "pipe_01|pipe_02")
50 ;; We don't model all pipeline stages; we model the issue stage
51 ;; inasmuch as we allow only two instructions to issue simultaneously,
52 ;; and flow instructions prevent any simultaneous issue of another instruction.
54 ;; Double issue of 'other' insns is prevented by using the int unit in the
56 ;; Double issue of float instructions is prevented by using F0 in the E1 stage.
62 "issue,int")
71 "issue,issue+int,int")
[all …]
|
| /netbsd-src/external/gpl3/gcc.old/dist/gcc/config/epiphany/ |
| H A D | epiphany-sched.md | 27 ;; Since epiphany is a dual issue machine, it is as if there are two
42 ;; This reservation is to simplify the dual issue description.
44 (define_reservation "issue" "pipe_01|pipe_02")
50 ;; We don't model all pipeline stages; we model the issue stage
51 ;; inasmuch as we allow only two instructions to issue simultaneously,
52 ;; and flow instructions prevent any simultaneous issue of another instruction.
54 ;; Double issue of 'other' insns is prevented by using the int unit in the
56 ;; Double issue of float instructions is prevented by using F0 in the E1 stage.
62 "issue,int")
71 "issue,issue+int,int")
[all …]
|
| /netbsd-src/external/gpl3/gcc/dist/gcc/config/sh/ |
| H A D | sh4.md | 47 ;; Since SH4 is a dual issue machine,it is as if there are two
70 ;; complete in 0 cycles. So we use an extra unit for the issue of LS insns.
74 ;; This will be reserved after "issue" of branch instructions
81 ;; This reservation is to simplify the dual issue description.
82 (define_reservation "issue" "pipe_01|pipe_02")
85 ;; Note that the issue of a CO group insn also effectively locks the D stage.
88 ;; Every FE instruction but fipr / ftrv starts with issue and this.
109 "issue")
115 "issue+load_store")
117 ;; We don't model all pipeline stages; we model the issue ('D') stage
[all …]
|
| /netbsd-src/external/gpl3/gcc.old/dist/gcc/config/sh/ |
| H A D | sh4.md | 47 ;; Since SH4 is a dual issue machine,it is as if there are two
70 ;; complete in 0 cycles. So we use an extra unit for the issue of LS insns.
74 ;; This will be reserved after "issue" of branch instructions
81 ;; This reservation is to simplify the dual issue description.
82 (define_reservation "issue" "pipe_01|pipe_02")
85 ;; Note that the issue of a CO group insn also effectively locks the D stage.
88 ;; Every FE instruction but fipr / ftrv starts with issue and this.
109 "issue")
115 "issue+load_store")
117 ;; We don't model all pipeline stages; we model the issue ('D') stage
[all …]
|
| /netbsd-src/external/apache2/llvm/dist/llvm/docs/ |
| H A D | Security.rst | 16 …issue reporter and key experts) while an issue is being investigated. After an issue becomes publi…
18 .. _report-security-issue:
20 How to report a security issue?
23 To report a security issue in the LLVM Project, please `open a new issue`_ in the LLVM project page…
25 …ion mailing list is public**: avoid discussing or mentioning the specific issue when posting on it.
76 …- If already in the LLVM Security Group, has actively participated in one (if any) security issue …
127 Members of the LLVM Security Group will be expected to treat LLVM security issue information shared…
129 * Members should not disclose security issue information to non-members unless both members are emp…
130 …ducts if their product suffers from the same issue. The non-LLVM vendor should be asked to respect…
131 … address particular issues. The key expert should be asked to respect the issue’s embargo date, an…
[all …]
|
| /netbsd-src/external/gpl3/gcc/dist/gcc/config/mips/ |
| H A D | 5k.md | 9 ;; 5Kc - Single issue with no floating point unit.
10 ;; 5kf - Separate floating point pipe which can dual-issue with the
117 ;; Any -> JR/JALR (without dependency) : 1 clock issue delay
118 ;; Any -> JR/JALR (with dependency) : 2 clock issue delay
119 ;; load -> JR/JALR (with dependency) : 3 clock issue delay
120 ;; mfhilo -> JR/JALR (with dependency) : 3 clock issue delay
121 ;; mul -> JR/JALR (with dependency) : 3 clock issue delay
127 ;; Unknown or multi - single issue
135 ;; The 5Kf is a partial dual-issue cpu which can dual issue an integer
225 ;; fxfer (mfc1, mfhc1, mtc1, mthc1) - single issue
|
| H A D | sb1.md | 24 ;; pipes, and 1 MDMX pipes. It can issue 2 ls insns and 2 exe/fpu/mdmx insns
27 ;; We model the 4-way issue by ordering unit choices. The possible choices are
28 ;; {ex1,fp1}|{ex0,fp0}|ls1|ls0. Instructions issue to the first eligible unit
29 ;; in the list in most cases. Non-indexed load/stores issue to ls0 first.
30 ;; simple alu operations issue to ls1 if it is still available, and their
31 ;; operands are ready (no co-issue with loads), otherwise to the first
34 ;; When exceptions are enabled, can only issue FP insns to fp1. This is
38 ;; In 32-bit mode, dependent FP can't co-issue with load, and only one FP exe
39 ;; insn can issue per cycle (fp1).
70 ;; Can only issue to one of the ex and fp pipes at a time.
[all …]
|
| /netbsd-src/external/gpl3/gcc.old/dist/gcc/config/mips/ |
| H A D | 5k.md | 9 ;; 5Kc - Single issue with no floating point unit.
10 ;; 5kf - Separate floating point pipe which can dual-issue with the
117 ;; Any -> JR/JALR (without dependency) : 1 clock issue delay
118 ;; Any -> JR/JALR (with dependency) : 2 clock issue delay
119 ;; load -> JR/JALR (with dependency) : 3 clock issue delay
120 ;; mfhilo -> JR/JALR (with dependency) : 3 clock issue delay
121 ;; mul -> JR/JALR (with dependency) : 3 clock issue delay
127 ;; Unknown or multi - single issue
135 ;; The 5Kf is a partial dual-issue cpu which can dual issue an integer
225 ;; fxfer (mfc1, mfhc1, mtc1, mthc1) - single issue
|
| H A D | sb1.md | 24 ;; pipes, and 1 MDMX pipes. It can issue 2 ls insns and 2 exe/fpu/mdmx insns
27 ;; We model the 4-way issue by ordering unit choices. The possible choices are
28 ;; {ex1,fp1}|{ex0,fp0}|ls1|ls0. Instructions issue to the first eligible unit
29 ;; in the list in most cases. Non-indexed load/stores issue to ls0 first.
30 ;; simple alu operations issue to ls1 if it is still available, and their
31 ;; operands are ready (no co-issue with loads), otherwise to the first
34 ;; When exceptions are enabled, can only issue FP insns to fp1. This is
38 ;; In 32-bit mode, dependent FP can't co-issue with load, and only one FP exe
39 ;; insn can issue per cycle (fp1).
70 ;; Can only issue to one of the ex and fp pipes at a time.
[all …]
|
| /netbsd-src/external/gpl3/gcc.old/dist/gcc/config/arm/ |
| H A D | cortex-a7.md | 80 ;; Cortex-A7 is in order and can dual-issue under limited circumstances.
103 ;; A direct branch can dual issue either as younger or older instruction,
104 ;; but branches cannot dual issue with branches.
112 ;; Call cannot dual-issue as an older instruction. It can dual-issue
113 ;; as a younger instruction, or single-issue. Call cannot dual-issue
125 ;; ALU instruction with an immediate operand can dual-issue.
134 ;; ALU instruction with register operands can dual-issue
169 ;; Multiply instructions cannot dual-issue.
193 ;; Address-generation happens in the issue stage.
242 ;; characteristics, but neon instructions cannot dual-issue.
[all …]
|
| H A D | cortex-a5.md | 28 ;; stages. However the decode/issue stages operate the same for all
31 ;; per cycle in order. Only branch instructions may dual-issue, so a
36 ;; The branch pipeline. Branches can dual-issue with other instructions
37 ;; (except when those instructions take multiple cycles to issue).
103 ;; Address-generation happens in the issue stage, which is one stage behind
155 ;; Direct branches are the only instructions we can dual-issue (also IT and
184 ;; We should try not to attempt to issue a single-precision multiplication in
195 ;; from F5 to F1. The issue unit is only used once (when we first start
205 ;; Non-multiply instructions can issue in the middle two instructions of a
207 ;; can dual-issue when a multi-cycle multiplication is in progress; we ignore
|
| /netbsd-src/external/gpl3/gcc/dist/gcc/config/arm/ |
| H A D | cortex-a7.md | 80 ;; Cortex-A7 is in order and can dual-issue under limited circumstances.
103 ;; A direct branch can dual issue either as younger or older instruction,
104 ;; but branches cannot dual issue with branches.
112 ;; Call cannot dual-issue as an older instruction. It can dual-issue
113 ;; as a younger instruction, or single-issue. Call cannot dual-issue
125 ;; ALU instruction with an immediate operand can dual-issue.
134 ;; ALU instruction with register operands can dual-issue
169 ;; Multiply instructions cannot dual-issue.
193 ;; Address-generation happens in the issue stage.
242 ;; characteristics, but neon instructions cannot dual-issue.
[all …]
|
| H A D | cortex-a5.md | 28 ;; stages. However the decode/issue stages operate the same for all
31 ;; per cycle in order. Only branch instructions may dual-issue, so a
36 ;; The branch pipeline. Branches can dual-issue with other instructions
37 ;; (except when those instructions take multiple cycles to issue).
103 ;; Address-generation happens in the issue stage, which is one stage behind
155 ;; Direct branches are the only instructions we can dual-issue (also IT and
184 ;; We should try not to attempt to issue a single-precision multiplication in
195 ;; from F5 to F1. The issue unit is only used once (when we first start
205 ;; Non-multiply instructions can issue in the middle two instructions of a
207 ;; can dual-issue when a multi-cycle multiplication is in progress; we ignore
|
| H A D | cortex-a8.md | 50 ;; ...and in the case of two micro-ops. Dual issue is altogether forbidden
51 ;; during the issue cycle of the first micro-op. (Instead of modelling
52 ;; a separate issue unit, we instead reserve alu0 and alu1 to
55 ;; ALU pipe, multi-cycle instructions always issue in pipeline 0.
66 ;; successive cycles. Dual issue cannot happen at the same time as the
73 ;; decomposed into three micro-ops. Dual issue cannot occur except on
174 ;; such instructions can issue back-to-back.
214 ;; offsets that are not LSL #2 have an extra cycle latency (they issue
|
| /netbsd-src/external/gpl3/gcc/dist/gcc/config/alpha/ |
| H A D | ev6.md | 20 ; EV6 can issue 4 insns per clock. It's out-of-order, so this isn't
30 ; all EBOX insn_reservations that can issue to either cluster, increasing
33 ; ??? In addition, instruction order affects cluster issue.
51 ; Integer loads take at least 3 clocks, and only issue to lower units.
92 ; Motion video insns also issue only to U0, and take three ticks.
98 ; Shifts issue to upper units.
104 ; Multiplies issue only to U1, and all take 7 ticks.
117 ; Integer branches issue to upper units
123 ; Calls only issue to L0.
129 ; Ftoi/itof only issue to lower pipes.
|
| /netbsd-src/external/gpl3/gcc.old/dist/gcc/config/alpha/ |
| H A D | ev6.md | 20 ; EV6 can issue 4 insns per clock. It's out-of-order, so this isn't
30 ; all EBOX insn_reservations that can issue to either cluster, increasing
33 ; ??? In addition, instruction order affects cluster issue.
51 ; Integer loads take at least 3 clocks, and only issue to lower units.
92 ; Motion video insns also issue only to U0, and take three ticks.
98 ; Shifts issue to upper units.
104 ; Multiplies issue only to U1, and all take 7 ticks.
117 ; Integer branches issue to upper units
123 ; Calls only issue to L0.
129 ; Ftoi/itof only issue to lower pipes.
|
| /netbsd-src/external/apache2/argon2/dist/phc-winner-argon2/ |
| H A D | CHANGELOG.md | 6 * Minor bug and warning fixes (no security issue)
13 * Minor bug fixes (no security issue)
23 * Minor bug and warning fixes (no security issue)
32 * Minor bug and warning fixes (no security issue)
|
| /netbsd-src/crypto/external/bsd/heimdal/dist/tests/kdc/ |
| H A D | check-pkinit.in | 122 ${hxtool} issue-certificate \
124 --issue-ca \
130 ${hxtool} issue-certificate \
138 ${hxtool} issue-certificate \
146 ${hxtool} issue-certificate \
153 ${hxtool} issue-certificate \
161 ${hxtool} issue-certificate \
|
| /netbsd-src/crypto/external/bsd/heimdal/dist/lib/hdb/ |
| H A D | hdb.schema | 18 #-- forwardable(1), -- may issue forwardable
19 #-- proxiable(2), -- may issue proxiable
20 #-- renewable(3), -- may issue renewable
21 #-- postdate(4), -- may issue postdatable
|
| /netbsd-src/external/lgpl3/gmp/dist/mpn/alpha/ |
| H A D | README | 88 store, no ld can issue.
90 2. mulq has a latency of 12 cycles and an issue rate of 1 each 8th cycle.
91 umulh has a latency of 14 cycles and an issue rate of 1 each 10th cycle.
96 ceil(37/2) [dual issue] + 1 [taken branch] = 19 cycles
98 cache cycles, which should be completely hidden in the 19 issue cycles.
113 a cmoveq/cmovne, which could issue one cycle earlier that the `or', but that
125 is currently instruction issue bound, Montgomery's idea should save us 1/2
143 multiply instruction can issue each cycle. To get optimal speed, we need to
163 Perhaps the most important issue is the latency between the L0/U0 and L1/U1
|
| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/ |
| H A D | AArch64SchedKryo.td | 15 // The issue width is set to five, matching the five issue queues for expanded
17 // but these do not actually take up an issue queue.
20 let IssueWidth = 5; // 5-wide issue for expanded uops
21 let MicroOpBufferSize = 128; // Out-of-order with temporary unified issue buffer
|