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Searched refs:isWave32 (Results 1 – 25 of 28) sorted by relevance

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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
H A DSIRegisterInfo.h33 bool isWave32; variable
279 return isWave32 ? &AMDGPU::SReg_32RegClass in getBoolRC()
284 return isWave32 ? &AMDGPU::SReg_32_XM0_XEXECRegClass in getWaveMaskRegClass()
H A DSIOptimizeExecMasking.cpp64 Src.getReg() == (ST.isWave32() ? AMDGPU::EXEC_LO : AMDGPU::EXEC)) in isCopyFromExec()
80 Dst.getReg() == (ST.isWave32() ? AMDGPU::EXEC_LO : AMDGPU::EXEC) && in isCopyToExec()
302 MCRegister Exec = ST.isWave32() ? AMDGPU::EXEC_LO : AMDGPU::EXEC; in runOnMachineFunction()
H A DSILateBranchLowering.cpp124 MovOpc = ST.isWave32() ? AMDGPU::S_MOV_B32 : AMDGPU::S_MOV_B64; in runOnMachineFunction()
125 ExecReg = ST.isWave32() ? AMDGPU::EXEC_LO : AMDGPU::EXEC; in runOnMachineFunction()
H A DAMDGPUAtomicOptimizer.cpp311 if (ST->isWave32()) in buildReduction()
366 if (!ST->isWave32()) { in buildScan()
411 if (!ST->isWave32()) { in buildShiftRight()
504 if (ST->isWave32()) { in optimizeAtomic()
H A DSIFrameLowering.cpp559 if (ST.isWave32()) { in emitEntryFunctionScratchRsrcRegSetup()
709 ST.isWave32() ? AMDGPU::S_OR_SAVEEXEC_B32 : AMDGPU::S_OR_SAVEEXEC_B64; in buildScratchExecCopy()
786 unsigned ExecMov = ST.isWave32() ? AMDGPU::S_MOV_B32 : AMDGPU::S_MOV_B64; in emitPrologue()
787 MCRegister Exec = ST.isWave32() ? AMDGPU::EXEC_LO : AMDGPU::EXEC; in emitPrologue()
1089 unsigned ExecMov = ST.isWave32() ? AMDGPU::S_MOV_B32 : AMDGPU::S_MOV_B64; in emitEpilogue()
1090 MCRegister Exec = ST.isWave32() ? AMDGPU::EXEC_LO : AMDGPU::EXEC; in emitEpilogue()
H A DSIRegisterInfo.cpp275 SpillSGPRToVGPR(EnableSpillSGPRToVGPR), isWave32(ST.isWave32()) { in SIRegisterInfo()
492 if (isWave32) { in getReservedRegs()
1308 SGPRSpillBuilder SB(*this, *ST.getInstrInfo(), isWave32, MI, Index, RS); in spillSGPR()
1406 SGPRSpillBuilder SB(*this, *ST.getInstrInfo(), isWave32, MI, Index, RS); in restoreSGPR()
1772 if (!isWave32) in eliminateFrameIndex()
2334 return isWave32 ? &AMDGPU::SReg_32_XM0_XEXECRegClass in getRegClassForSizeOnBank()
2357 return isWave32 ? AMDGPU::VCC_LO : AMDGPU::VCC; in getVCC()
2372 return isWave32 ? &AMDGPU::SReg_32_XM0_XEXECRegClass in getRegClass()
H A DSIInstrInfo.cpp1071 BuildMI(MBB, I, DL, get(ST.isWave32() ? AMDGPU::S_CSELECT_B32 in insertVectorSelect()
1085 BuildMI(MBB, I, DL, get(ST.isWave32() ? AMDGPU::S_CSELECT_B32 in insertVectorSelect()
1128 BuildMI(MBB, I, DL, get(ST.isWave32() ? AMDGPU::S_OR_SAVEEXEC_B32 in insertVectorSelect()
1131 BuildMI(MBB, I, DL, get(ST.isWave32() ? AMDGPU::S_CSELECT_B32 in insertVectorSelect()
1146 BuildMI(MBB, I, DL, get(ST.isWave32() ? AMDGPU::S_OR_SAVEEXEC_B32 in insertVectorSelect()
1149 BuildMI(MBB, I, DL, get(ST.isWave32() ? AMDGPU::S_CSELECT_B32 in insertVectorSelect()
1757 unsigned NotOpc = ST.isWave32() ? AMDGPU::S_NOT_B32 : AMDGPU::S_NOT_B64; in expandPostRAPseudo()
1758 unsigned Exec = ST.isWave32() ? AMDGPU::EXEC_LO : AMDGPU::EXEC; in expandPostRAPseudo()
1769 unsigned NotOpc = ST.isWave32() ? AMDGPU::S_NOT_B32 : AMDGPU::S_NOT_B64; in expandPostRAPseudo()
1770 unsigned Exec = ST.isWave32() ? AMDGPU::EXEC_LO : AMDGPU::EXEC; in expandPostRAPseudo()
[all …]
H A DSILowerI1Copies.cpp420 return MRI.createVirtualRegister(ST.isWave32() ? &AMDGPU::SReg_32RegClass in createLaneMaskReg()
456 IsWave32 = ST->isWave32(); in runOnMachineFunction()
H A DSILowerControlFlow.cpp637 bool IsWave32 = ST.isWave32(); in lowerInitExec()
782 if (ST.isWave32()) { in runOnMachineFunction()
H A DSIAnnotateControlFlow.cpp127 IntMask = ST.isWave32() ? Type::getInt32Ty(Context) in initialize()
H A DSIPreEmitPeephole.cpp80 const bool IsWave32 = ST.isWave32(); in optimizeVccBranch()
H A DSIWholeQuadMode.cpp873 Register VCC = ST->isWave32() ? AMDGPU::VCC_LO : AMDGPU::VCC; in lowerKillF32()
976 unsigned MovOpc = ST->isWave32() ? AMDGPU::S_MOV_B32 : AMDGPU::S_MOV_B64; in lowerKillI1()
1522 if (ST->isWave32()) { in runOnMachineFunction()
H A DGCNSubtarget.h1090 bool isWave32() const { in isWave32() function
H A DSIOptimizeExecMaskingPreRA.cpp314 const bool Wave32 = ST.isWave32(); in runOnMachineFunction()
H A DVOP2Instructions.td213 let WaveSizePredicate = isWave32 in {
258 let WaveSizePredicate = isWave32 in {
1073 let WaveSizePredicate = isWave32;
1100 let WaveSizePredicate = isWave32;
1125 let WaveSizePredicate = isWave32;
H A DAMDGPUAsmPrinter.cpp415 if (MF.getSubtarget<GCNSubtarget>().isWave32()) { in getAmdhsaKernelCodeProperties()
1357 if (STM.isWave32()) in EmitPALMetadata()
H A DVOPCInstructions.td169 let WaveSizePredicate = isWave32 in {
769 let WaveSizePredicate = isWave32 in
818 let WaveSizePredicate = isWave32 in
H A DSIShrinkInstructions.cpp601 unsigned VCCReg = ST.isWave32() ? AMDGPU::VCC_LO : AMDGPU::VCC; in runOnMachineFunction()
H A DAMDGPURegisterBankInfo.cpp721 const unsigned WaveAndOpc = Subtarget.isWave32() ? in executeInWaterfallLoop()
723 const unsigned MovTermOpc = Subtarget.isWave32() ? in executeInWaterfallLoop()
725 const unsigned XorTermOpc = Subtarget.isWave32() ? in executeInWaterfallLoop()
727 const unsigned AndSaveExecOpc = Subtarget.isWave32() ? in executeInWaterfallLoop()
729 const unsigned ExecReg = Subtarget.isWave32() ? in executeInWaterfallLoop()
H A DSIInstructions.td253 let WaveSizePredicate = isWave32 in {
1576 let WaveSizePredicate = isWave32;
1909 let WaveSizePredicate = isWave32 in {
1946 } // end isWave32
H A DSIInstrInfo.h1051 bool isWave32() const;
H A DSIInsertWaitcnts.cpp1562 TII->get(ST->isWave32() ? AMDGPU::S_MOV_B32 : AMDGPU::S_MOV_B64), in insertWaitcntInBlock()
H A DAMDGPUISelDAGToDAG.cpp2292 Cond = SDValue(CurDAG->getMachineNode(ST->isWave32() ? AMDGPU::S_AND_B32 in SelectBRCOND()
2295 CurDAG->getRegister(ST->isWave32() ? AMDGPU::EXEC_LO in SelectBRCOND()
H A DSIISelLowering.cpp3533 BuildMI(LoopBB, I, DL, TII->get(ST.isWave32() ? AMDGPU::S_AND_SAVEEXEC_B32 in emitLoadM0FromVGPRLoop()
3562 unsigned Exec = ST.isWave32() ? AMDGPU::EXEC_LO : AMDGPU::EXEC; in emitLoadM0FromVGPRLoop()
3564 BuildMI(LoopBB, I, DL, TII->get(ST.isWave32() ? AMDGPU::S_XOR_B32_term in emitLoadM0FromVGPRLoop()
3599 unsigned Exec = ST.isWave32() ? AMDGPU::EXEC_LO : AMDGPU::EXEC; in loadM0FromVGPR()
3600 unsigned MovExecOpc = ST.isWave32() ? AMDGPU::S_MOV_B32 : AMDGPU::S_MOV_B64; in loadM0FromVGPR()
11790 if (ST.isWave32() && !MF.empty()) { in finalizeLowering()
H A DVOP3Instructions.td752 let WaveSizePredicate = isWave32 in {

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