| /netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/ |
| H A D | ProcessImplicitDefs.cpp | 70 if (MO.isReg() && MO.isUse() && MO.readsReg()) in canTurnIntoImplicitDef()
110 if (MO.isUse()) in processImplicitDef()
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| H A D | MachineLoopInfo.cpp | 168 if (MO.isUse()) { in isLoopInvariant()
189 if (!MO.isUse()) in isLoopInvariant()
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| H A D | TwoAddressInstructionPass.cpp | 255 if (MO.isUse() && DI->second < LastUse) in noUseAfterLastDef()
363 if (!MO.isReg() || !MO.isUse() || MO.getReg() != Reg) in isTwoAddrUse()
955 if (MO.isUse()) { in rescheduleKillAboveMI()
994 if (MO.isUse()) { in rescheduleKillAboveMI()
1256 if (MO.isUse()) { in tryInstructionTransform()
1335 assert(SrcReg && SrcMO.isUse() && "two address instruction invalid"); in collectTiedOperands()
1444 assert(MO.isReg() && MO.getReg() == RegB && MO.isUse() && in processTiedPairs()
1469 if (MO.isReg() && MO.getReg() == RegB && MO.isUse()) { in processTiedPairs()
1509 if (MO.isReg() && MO.getReg() == RegB && MO.isUse()) { in processTiedPairs()
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| H A D | MachineInstr.cpp | 288 if (NewMO->isUse()) { in addOperand()
896 if (getOperand(OpIdx).isUse() && isRegTiedToDefOperand(OpIdx, &DefIdx)) in getRegClassConstraint()
983 if (MO.isReg() && MO.isUse() && MO.isImplicit() && MO.getReg() == Reg) in hasRegisterImplicitUseOperand()
996 if (!MO.isReg() || !MO.isUse()) in findRegisterUseOperandIdx()
1024 if (MO.isUse()) in readsWritesVirtualRegister()
1103 assert(UseMO.isUse() && "UseIdx must be a use operand"); in tieOperands()
1137 if (MO.isUse()) in findTiedOperandIdx()
1142 if (UseMO.isReg() && UseMO.isUse() && UseMO.TiedTo == OpIdx + 1) in findTiedOperandIdx()
1204 if (MO.isReg() && MO.isUse()) in clearKillInfo()
1478 if (!MO.isReg() || MO.isUse()) in allDefsAreDead()
[all …]
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| H A D | BreakFalseDeps.cpp | 195 if (!MO.isReg() || !MO.getReg() || !MO.isUse() || !MO.isUndef()) in processDefs()
220 if (MO.isUse()) in processDefs()
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| H A D | LiveIntervals.cpp | 789 if (MO.isUse()) { in addKillFlags()
863 float LiveIntervals::getSpillWeight(bool isDef, bool isUse, in getSpillWeight() argument
866 return getSpillWeight(isDef, isUse, MBFI, MI.getParent()); in getSpillWeight()
869 float LiveIntervals::getSpillWeight(bool isDef, bool isUse, in getSpillWeight() argument
872 return (isDef + isUse) * MBFI->getBlockFreqRelativeToEntryBlock(MBB); in getSpillWeight()
1017 if (MO.isUse()) { in updateAllRanges()
1116 if (MOP.isReg() && MOP.isUse()) in handleMoveDown()
1417 if (MO->isReg() && !MO->isUse()) in handleMoveUp()
1643 } else if (MO.isUse()) { in repairOldRegInRange()
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| H A D | CriticalAntiDepBreaker.cpp | 237 if (MO.isUse() && Special) { in PrescanInstruction()
313 if (!MO.isUse()) continue; in ScanInstruction()
622 if (MO.isUse() && TRI->regsOverlap(AntiDepReg, Reg)) { in BreakAntiDependencies()
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| H A D | MachineCSE.cpp | 170 if (!MO.isReg() || !MO.isUse()) in INITIALIZE_PASS_DEPENDENCY()
242 if (MO.isUse()) in isPhysDefTriviallyDead()
467 if (MO.isReg() && MO.isUse() && Register::isVirtualRegister(MO.getReg())) { in isProfitableToCSE()
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| H A D | RegisterScavenging.cpp | 141 if (MO.isUse()) { in determineKillsAndDefs()
191 if (MO.isUse()) { in forward()
531 if (MO.isReg() && MO.getReg() != 0 && !(MO.isUse() && MO.isUndef()) && in scavengeRegister()
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| H A D | DeadMachineInstructionElim.cpp | 180 if (MO.isReg() && MO.isUse()) { in eliminateDeadMI()
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| H A D | MachineSink.cpp | 602 if (!MO.isReg() || !MO.isUse()) in isWorthBreakingCriticalEdge()
905 if (MO.isUse()) { in FindSuccToSinkTo()
917 if (MO.isUse()) continue; in FindSuccToSinkTo()
1441 if (MO.isReg() && MO.isUse()) in SinkInstruction()
1679 } else if (MO.isUse()) { in hasRegisterDependency()
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| H A D | ExpandPostRAPseudos.cpp | 80 (MI->getOperand(2).isReg() && MI->getOperand(2).isUse()) && in LowerSubregToReg()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Sparc/ |
| H A D | DelaySlotFiller.cpp | 263 if (MO.isUse()) { in delayHasHazard()
304 assert(Reg.isUse() && "CALL first operand is not a use."); in insertCallDefsUses()
311 assert(Operand1.isUse() && "CALLrr second operand is not a use."); in insertCallDefsUses()
332 if (MO.isUse()) { in insertDefsUses()
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| /netbsd-src/external/apache2/llvm/dist/llvm/tools/llvm-exegesis/lib/ |
| H A D | MCInstrDescView.cpp | 46 bool Operand::isUse() const { return !IsDef; } in isUse() function in llvm::exegesis::Operand
177 if (Op.isUse()) in create()
181 if (Op.isUse() && Op.isImplicit()) in create()
260 if (Op.isUse()) in dump()
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| H A D | MCInstrDescView.h | 71 bool isUse() const;
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Lanai/ |
| H A D | LanaiDelaySlotFiller.cpp | 215 if (MO.isUse()) { in delayHasHazard()
241 else if (MO.isUse()) in insertDefsUses()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/ |
| H A D | HexagonNewValueJump.cpp | 178 (II->getOperand(i).isUse() || II->getOperand(i).isDef())) { in INITIALIZE_PASS_DEPENDENCY()
653 if (!MO.isReg() || !MO.isUse()) in runOnMachineFunction()
660 if (!Op.isReg() || !Op.isUse() || !Op.isKill()) in runOnMachineFunction()
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| H A D | HexagonGenPredicate.cpp | 260 assert(DefI->getOperand(0).isDef() && DefI->getOperand(1).isUse()); in getPredRegFor()
356 if (MO.isReg() && MO.isUse()) in isScalarPred()
377 if (!MO.isReg() || !MO.isUse()) in convertToPredForm()
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| H A D | HexagonSubtarget.cpp | 312 if (MO.isUse() && !MI->isCopy() && in apply()
423 if (MO.isReg() && MO.getReg() && MO.isUse() && MO.getReg() == DReg) { in adjustSchedDependency()
515 if (MO.isReg() && MO.isUse() && MO.getReg() == DepR) { in restoreLatency()
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| /netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/ |
| H A D | LiveIntervals.h | 105 static float getSpillWeight(bool isDef, bool isUse,
110 static float getSpillWeight(bool isDef, bool isUse,
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| H A D | MachineRegisterInfo.h | 1005 if ((!ReturnUses && op->isUse()) || in defusechain_iterator()
1019 if (Op->isUse()) in advance()
1113 if ((!ReturnUses && op->isUse()) || in defusechain_instr_iterator()
1127 if (Op->isUse()) in advance()
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| H A D | LiveRegUnits.h | 66 assert(O->isUse() && "Reg operand not a def and not a use"); in accumulateUsedDefed()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/X86/ |
| H A D | X86FixupBWInsts.cpp | 263 assert((MO.isDef() || MO.isUse()) && "Expected Def or Use only!"); in getSuperRegDestIfDead()
272 if (MO.isUse() && !TRI->isSubRegisterEq(OrigDestReg, MO.getReg()) && in getSuperRegDestIfDead()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/BPF/ |
| H A D | BPFMIChecking.cpp | 115 if (!MO.isReg() || MO.isUse()) in hasLiveDefs()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/WebAssembly/ |
| H A D | WebAssemblyRegColoring.cpp | 70 Weight += LiveIntervals::getSpillWeight(MO.isDef(), MO.isUse(), MBFI, in computeWeight()
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