Searched refs:isOptionalDef (Results 1 – 13 of 13) sorted by relevance
111 bool isOptionalDef() const { return Flags & (1 << MCOI::OptionalDef); } in isOptionalDef() function
242 && !DefMI->getDesc().OpInfo[DefOperIdx].isOptionalDef() in computeOperandLatency()
1792 else if (!MO->isDef() && !MCOI.isOptionalDef()) in visitMachineOperand()1803 if (MO->isDef() && !MCOI.isOptionalDef() && !MCID.variadicOpsAreDefs()) in visitMachineOperand()
105 if (IsDef && !OpInfo.isOptionalDef()) in addInstruction()
841 if (i < NumOps && MCID.OpInfo[i].isOptionalDef()) in ReduceTo2Addr()948 if (i < NumOps && MCID.OpInfo[i].isOptionalDef()) in ReduceToNarrow()
594 assert(MCID.OpInfo[1].isOptionalDef() && "CPSR def isn't expected operand"); in PredicateInstruction()
11717 if (!MI.hasOptionalDef() || !MCID->OpInfo[ccOutIdx].isOptionalDef()) { in AdjustInstrPostInstrSelection()
227 if (II.OpInfo != nullptr && II.OpInfo[i].isOptionalDef()) { in CreateVirtualRegisters()313 MCID.OpInfo[IIOpNum].isOptionalDef(); in AddRegisterOperand()
1419 if (MCID.OpInfo[i].isOptionalDef()) { in DelayForLiveRegsBottomUp()
192 Desc.OpInfo[I].isOptionalDef()) in isCPSRDefined()
319 if (MCDesc.OpInfo[CurrentDef].isOptionalDef()) { in populateWrites()
737 if (OpInfo[i].isOptionalDef() && OpInfo[i].RegClass == ARM::CCRRegClassID) { in AddThumb1SBit()
10701 !MCID.OpInfo[OpNo].isOptionalDef() && OpNo < MCID.NumOperands; in checkTargetMatchPredicate()