Searched refs:isInsertSubreg (Results 1 – 16 of 16) sorted by relevance
104 } else if (DefMI->isInsertSubreg()) { in getAccDefMI()126 while (UseMI->isCopy() || UseMI->isInsertSubreg()) { in getDefReg()168 } else if (DefMI->isInsertSubreg()) { in hasLoopHazard()
246 if (MI->isInsertSubreg()) { in optimizeSDPattern()329 if (MI->isInsertSubreg() && usesRegClass(MI->getOperand(2), in hasPartialWrite()396 if (MI->isCopyLike() || MI->isInsertSubreg() || MI->isRegSequence() || in getReadDPRs()
4347 if (ResolvedDefMI->isCopyLike() || ResolvedDefMI->isInsertSubreg() || in getOperandLatency()4686 if (MI.isCopyLike() || MI.isInsertSubreg() || MI.isRegSequence() || in getPredicationCost()4707 if (MI.isCopyLike() || MI.isInsertSubreg() || MI.isRegSequence() || in getInstrLatency()
1832 let isInsertSubreg = 1 in
6461 let isInsertSubreg = 1;
65 !MI->isInsertSubreg() && in canTurnIntoImplicitDef()
244 (MI.isRegSequence() || MI.isInsertSubreg() || in isCoalescableCopy()912 assert(MI.isInsertSubreg() && "Invalid instruction"); in InsertSubregRewriter()1924 assert((Def->isInsertSubreg() || Def->isInsertSubregLike()) && in getNextSourceFromInsertSubreg()2067 if (Def->isInsertSubreg() || Def->isInsertSubregLike()) in getNextSourceImpl()
1338 assert((MI.isInsertSubreg() || in getInsertSubregInputs()1341 if (!MI.isInsertSubreg()) in getInsertSubregInputs()
275 } else if (MI.isInsertSubreg() || MI.isSubregToReg()) { in isCopyToReg()1615 if (mi->isInsertSubreg()) { in runOnMachineFunction()
137 FLAG(isInsertSubreg) in EmitInstrDocs()
275 bool isInsertSubreg : 1; variable
398 isInsertSubreg = R->getValueAsBit("isInsertSubreg"); in CodeGenInstruction()
982 if (Inst.isInsertSubreg) OS << "|(1ULL<<MCID::InsertSubreg)"; in emitRecord()
582 if (isInsertSubreg() && OpIdx == 3)1263 bool isInsertSubreg() const {
563 bit isInsertSubreg = false; // Is this instruction a kind of insert subreg?
1932 bit isInsertSubreg = 0;