| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
| H A D | SIInstrInfo.h | 754 bool isInlineConstant(const APInt &Imm) const;
756 bool isInlineConstant(const APFloat &Imm) const { in isInlineConstant() function
757 return isInlineConstant(Imm.bitcastToAPInt()); in isInlineConstant()
760 bool isInlineConstant(const MachineOperand &MO, uint8_t OperandType) const;
762 bool isInlineConstant(const MachineOperand &MO, in isInlineConstant() function
764 return isInlineConstant(MO, OpInfo.OperandType); in isInlineConstant()
769 bool isInlineConstant(const MachineInstr &MI, in isInlineConstant() function
778 return isInlineConstant(DefMO, MI.getDesc().OpInfo[OpIdx]); in isInlineConstant()
783 bool isInlineConstant(const MachineInstr &MI, unsigned OpIdx) const { in isInlineConstant() function
785 return isInlineConstant(MO, MI.getDesc().OpInfo[OpIdx].OperandType); in isInlineConstant()
[all …]
|
| H A D | SIShrinkInstructions.cpp | 119 !TII->isInlineConstant(*Src.getParent(), in isKImmOperand()
125 !TII->isInlineConstant(*Src.getParent(), in isKUImmOperand()
134 return !TII->isInlineConstant(Src); in isKImmOrKUImmOperand()
139 return !TII->isInlineConstant(Src); in isKImmOrKUImmOperand()
150 if (!isInt<32>(Src.getImm()) || TII->isInlineConstant(Src)) in isReverseInlineImm()
|
| H A D | SIFoldOperands.cpp | 154 if (TII->isInlineConstant(UseMI, OpNo, OpToFold)) in isInlineConstantIfFolded()
165 return TII->isInlineConstant(OpToFold, MadDesc.OpInfo[OpNo].OperandType); in isInlineConstantIfFolded()
456 !TII->isInlineConstant(*OpToFold, OpInfo)) { in tryAddToFoldList()
514 if (TII->isInlineConstant(*Op, OpTy)) in getRegSeqInit()
546 if (OpToFold.isImm() && TII->isInlineConstant(OpToFold, OpTy) && in tryToFoldACImm()
569 if (DefOp.isImm() && TII->isInlineConstant(DefOp, OpTy) && in tryToFoldACImm()
589 if (!TII->isInlineConstant(*Op, OpTy) || in tryToFoldACImm()
713 TII->isInlineConstant(OpToFold, AMDGPU::OPERAND_REG_INLINE_C_INT32)) { in foldOperand()
772 TII->isInlineConstant(*Def, AMDGPU::OPERAND_REG_INLINE_C_INT32)) { in foldOperand()
|
| H A D | AMDGPUISelDAGToDAG.cpp | 160 return Subtarget->getInstrInfo()->isInlineConstant(Imm); in isInlineImmediate()
532 return TII->isInlineConstant(-C->getAPIntValue()); in isInlineImmediate()
535 return TII->isInlineConstant(-C->getValueAPF().bitcastToAPInt()); in isInlineImmediate()
539 return TII->isInlineConstant(C->getAPIntValue()); in isInlineImmediate()
542 return TII->isInlineConstant(C->getValueAPF().bitcastToAPInt()); in isInlineImmediate()
1825 !TII->isInlineConstant(APInt(32, COffsetVal & 0xffffffff)) + in SelectGlobalSAddr()
1826 !TII->isInlineConstant(APInt(32, COffsetVal >> 32)); in SelectGlobalSAddr()
|
| H A D | SIInstrInfo.cpp | 1707 if (ST.hasPackedFP32Ops() && Lo == Hi && isInlineConstant(Lo)) { in expandPostRAPseudo()
2733 if (!isInlineConstant(Imm)) in FoldImmediate()
2775 if (isInlineConstant(UseMI, *Src0, *ImmOp)) in FoldImmediate()
2849 isInlineConstant(Def->getOperand(1)) && in FoldImmediate()
2867 isInlineConstant(Def->getOperand(1)) && in FoldImmediate()
3077 if (Src0->isImm() && !isInlineConstant(MI, Src0Idx, *Src0)) in convertToThreeAddress()
3296 bool SIInstrInfo::isInlineConstant(const APInt &Imm) const { in isInlineConstant() function in SIInstrInfo
3316 bool SIInstrInfo::isInlineConstant(const MachineOperand &MO, in isInlineConstant() function in SIInstrInfo
3401 return !isInlineConstant(MO, OpInfo); in isLiteralConstantLike()
3441 if (MO.isImm() && isInlineConstant(MO, OpInfo)) { in isImmOperandLegal()
[all …]
|
| H A D | SIFixSGPRCopies.cpp | 744 TII->isInlineConstant(APInt(64, Copied.getImm(), true))) { in runOnMachineFunction()
|
| H A D | AMDGPUInstructionSelector.cpp | 2141 if (IsSgpr && TII.isInlineConstant(Imm)) { in selectG_CONSTANT()
3574 !TII.isInlineConstant(APInt(32, ConstOffset & 0xffffffff)) + in selectGlobalSAddr()
3575 !TII.isInlineConstant(APInt(32, ConstOffset >> 32)); in selectGlobalSAddr()
4398 return TII.isInlineConstant(Imm); in isInlineImmediate()
|
| H A D | SILoadStoreOptimizer.cpp | 1661 if (TII->isInlineConstant(V)) in createRegOrImm()
|
| H A D | SIISelLowering.cpp | 8920 (CRHS->hasOneUse() && !TII->isInlineConstant(CRHS->getAPIntValue()))) { in splitBinaryBitConstantOp()
9940 TII->isInlineConstant(K0->getValueAPF().bitcastToAPInt())) && in performFPMed3ImmCombine()
9942 TII->isInlineConstant(K1->getValueAPF().bitcastToAPInt()))) { in performFPMed3ImmCombine()
|
| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/AsmParser/ |
| H A D | AMDGPUAsmParser.cpp | 1555 bool isInlineConstant(const MCInst &Inst, unsigned OpIdx) const;
3155 bool AMDGPUAsmParser::isInlineConstant(const MCInst &Inst, in isInlineConstant() function in AMDGPUAsmParser
3221 return !isInlineConstant(Inst, OpIdx); in usesConstantBus()
3919 if (MO.isImm() && !isInlineConstant(Inst, OpIdx)) { in validateSOPLiteral()
4010 if (MO.isImm() && !isInlineConstant(Inst, OpIdx)) { in validateVOP3Literal()
|