/netbsd-src/external/apache2/llvm/dist/llvm/utils/TableGen/GlobalISel/ |
H A D | GIMatchDag.cpp | 62 if (E->getFromMO()->isDef() && !E->getToMO()->isDef()) in writeDOTGraph() 66 if (E->getFromMO()->isDef() && !E->getToMO()->isDef()) in writeDOTGraph() 70 if (E->getFromMO()->isDef() == E->getToMO()->isDef()) in writeDOTGraph() 73 if (E->getFromMO()->isDef() == E->getToMO()->isDef()) in writeDOTGraph() 75 else if (E->getFromMO()->isDef() && !E->getToMO()->isDef()) in writeDOTGraph()
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H A D | GIMatchDagOperands.cpp | 35 I.value().isDef()); in Profile() 46 if (I.isDef()) in print()
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/ |
H A D | LiveIntervalCalc.cpp | 65 if (!MO.isDef() && !MO.readsReg()) in calculate() 82 if (MO.isDef()) in calculate() 90 if (MO.isDef() && !LI.hasSubRanges()) in calculate() 165 if (!MO.readsReg() || (IsSubRange && MO.isDef())) in extendToUses() 171 if (MO.isDef()) in extendToUses() 183 assert(!MO.isDef() && "Cannot handle PHI def of partial register."); in extendToUses() 191 if (MO.isDef()) in extendToUses()
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H A D | MachineOperand.cpp | 94 if (isDef()) in substPhysReg() 129 if (isDef()) in isRenamable() 241 void MachineOperand::ChangeToRegister(Register Reg, bool isDef, bool isImp, in ChangeToRegister() argument 254 assert(!(isDead && !isDef) && "Dead flag on non-def"); in ChangeToRegister() 255 assert(!(isKill && isDef) && "Kill flag on def"); in ChangeToRegister() 259 IsDef = isDef; in ChangeToRegister() 289 return getReg() == Other.getReg() && isDef() == Other.isDef() && in isIdenticalTo() 355 return hash_combine(MO.getType(), (unsigned)MO.getReg(), MO.getSubReg(), MO.isDef()); in hash_value() 745 OS << (isDef() ? "implicit-def " : "implicit "); in print() 746 else if (PrintDef && isDef()) in print() [all …]
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H A D | RenameIndependentSubregs.cpp | 180 if (!MO.isDef() && !MO.readsReg()) in findComponents() 190 Pos = MO.isDef() ? Pos.getRegSlot(MO.isEarlyClobber()) in findComponents() 219 if (!MO.isDef() && !MO.readsReg()) in rewriteOperands() 224 Pos = MO.isDef() ? Pos.getRegSlot(MO.isEarlyClobber()) in rewriteOperands() 346 if (!MO.isDef()) in computeMainRangesFixFlags()
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H A D | LiveRangeEdit.cpp | 192 if (MO.isDef()) { in foldAsLoad() 293 if (VRM && MI->getOperand(0).isReg() && MI->getOperand(0).isDef() && in eliminateDeadDef() 317 else if (MOI->isDef()) in eliminateDeadDef() 327 if ((MI->readsVirtualRegister(Reg) && (MI->isCopy() || MOI->isDef())) || in eliminateDeadDef() 332 if (MOI->isDef()) { in eliminateDeadDef()
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H A D | MachineInstrBundle.cpp | 151 if (MO.isDef()) { in finalizeBundle() 294 if (MO.isDef()) in AnalyzeVirtRegInBundle() 299 if (MO.isDef()) in AnalyzeVirtRegInBundle() 340 } else if (MO.isDef()) { in AnalyzePhysRegInBundle()
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H A D | MIRCanonicalizerPass.cpp | 171 if (!MO.isDef()) in rescheduleCanonically() 187 if (!MO.isDef()) in rescheduleCanonically() 354 if (!MO.isDef() && MO.isKill()) { in doDefKillClear() 359 if (MO.isDef() && MO.isDead()) { in doDefKillClear()
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H A D | RegisterScavenging.cpp | 148 assert(MO.isDef()); in determineKillsAndDefs() 224 assert(MO.isDef()); in forward() 314 if (MO.isDef()) in findSurvivorReg() 624 if (MO.isDef()) { in scavengeVReg() 715 assert((!MO.isUndef() || MO.isDef()) && "Cannot handle undef uses"); in scavengeFrameVirtualRegsInBlock() 719 if (MO.isDef()) { in scavengeFrameVirtualRegsInBlock() 730 assert((!MO.isUndef() || MO.isDef()) && "Cannot handle undef uses"); in scavengeFrameVirtualRegsInBlock()
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H A D | ImplicitNullChecks.cpp | 295 if (TRI->regsOverlap(RegA, RegB) && (MOA.isDef() || MOB.isDef())) in canReorder() 742 assert(MO.isDef() && "Expected def or use"); in insertFaultingInstr() 784 if (!MO.isReg() || !MO.isDef()) in rewriteNullChecks() 794 if (!MO.isReg() || !MO.getReg() || !MO.isDef() || MO.isDead()) in rewriteNullChecks()
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H A D | CriticalAntiDepBreaker.cpp | 282 if (!MO.isDef()) continue; in ScanInstruction() 361 if (RefOper->isDef() && RefOper->isEarlyClobber()) in isNewRegClobberedByRefs() 372 if (!CheckOper.isReg() || !CheckOper.isDef() || in isNewRegClobberedByRefs() 378 if (RefOper->isDef()) in isNewRegClobberedByRefs() 626 if (MO.isDef() && Reg != AntiDepReg) in BreakAntiDependencies()
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H A D | LiveRegUnits.cpp | 48 if (MOP.isDef()) in stepBackward() 67 if (!MOP.isDef() && !MOP.readsReg()) in accumulate()
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H A D | MachineLICM.cpp | 456 if (!MO.isDef()) { in ProcessMI() 578 if (!MO.isReg() || MO.isDef() || !MO.getReg()) in HoistRegionPostRA() 603 if (!MO.isReg() || !MO.getReg() || MO.isDef()) continue; in AddToLiveIns() 844 if (MO.isDef()) in calcRegisterCost() 1005 if (!MO.isReg() || !MO.isDef()) in HasLoopPHIUse() 1074 if (!DefMO.isReg() || !DefMO.isDef()) in IsCheapInstruction() 1173 if (MO.isDef() && HasHighOperandLatency(MI, i, Reg)) { in IsProfitableToHoist() 1333 if (MO.isReg() && MO.isDef() && in EliminateCSE() 1448 if (MO.isReg() && MO.isDef() && !MO.isDead()) in Hoist()
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H A D | VirtRegMap.cpp | 560 if ((MO.readsReg() && (MO.isDef() || MO.isKill())) || in rewrite() 561 (MO.isDef() && subRegLiveThrough(*MI, PhysReg))) in rewrite() 564 if (MO.isDef()) { in rewrite() 579 assert(MO.isDef()); in rewrite() 587 if (MO.isDef()) { in rewrite()
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H A D | MachineInstr.cpp | 634 if (MO.isDef()) { in isIdenticalTo() 692 if (!MO.isReg() || !MO.isDef()) in eraseFromParentAndMarkDBGValuesForRemoval() 752 if (!MO.isReg() || !MO.isDef() || MO.isImplicit()) in getNumExplicitDefs() 1050 if (!MO.isReg() || !MO.isDef()) in findRegisterDefOperandIdx() 1102 assert(DefMO.isDef() && "DefIdx must be a def operand"); in tieOperands() 1504 if (!Operand.isReg() || Operand.isDef()) in hasComplexRegisterTies() 1558 if (!MO.isReg() || MO.isDef()) in dumprImpl() 1613 if (MO.isReg() && MO.isTied() && !MO.isDef()) in print() 1623 if (!MO.isReg() || !MO.isDef() || MO.isImplicit()) in print() 1967 if (!MO.isReg() || !MO.isDef()) in addRegisterDead() [all …]
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H A D | DeadMachineInstructionElim.cpp | 81 if (MO.isReg() && MO.isDef()) { in isDead() 161 if (MO.isReg() && MO.isDef()) { in eliminateDeadMI()
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H A D | LivePhysRegs.cpp | 52 if (MOP.isDef()) in removeDefs() 88 if (O->isDef()) { in stepForward() 289 if (!MO->isReg() || !MO->isDef() || MO->isDebug()) in recomputeLivenessFlags()
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H A D | MachineStableHash.cpp | 72 MO.isDef()); in stableHashValue() 163 if (!HashVRegs && MO.isReg() && MO.isDef() && in stableHashValue()
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H A D | MachineCSE.cpp | 284 if (!MO.isReg() || MO.isDef()) in hasLivePhysRegDefUses() 303 if (!MO.isReg() || !MO.isDef()) in hasLivePhysRegDefUses() 380 if (!MO.isReg() || !MO.isDef()) in PhysRegDefsReach() 614 if (!MO.isReg() || !MO.isDef()) in ProcessBlockCSE() 850 assert(MI->getOperand(0).isDef() && in ProcessBlockPRE()
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/GlobalISel/ |
H A D | RegBankSelect.cpp | 154 if (MO.isDef()) in repairReg() 175 if (MO.isDef()) { in repairReg() 247 assert(CurRegBank || MO.isDef()); in getRepairCost() 266 if (MO.isDef()) in getRepairCost() 339 assert((!MI.isPHI() || !MO.isDef()) && "Need split for phi def?"); in tryAvoidingSplit() 342 if (!MO.isDef()) { in tryAvoidingSplit() 366 assert(MI.isTerminator() && MO.isDef() && in tryAvoidingSplit() 766 bool Before = !MO.isDef(); in RepairingPlacement()
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/netbsd-src/external/apache2/llvm/dist/llvm/tools/llvm-exegesis/lib/ |
H A D | MCInstrDescView.cpp | 44 bool Operand::isDef() const { return IsDef; } in isDef() function in llvm::exegesis::Operand 175 if (Op.isDef()) in create() 179 if (Op.isDef() && Op.isImplicit()) in create() 262 if (Op.isDef()) in dump() 330 if (Op.isReg() && Op.isDef() == SelectDef) { in addOperandIfAlias()
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/netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/ |
H A D | MachineOperand.h | 375 bool isDef() const { in isDef() function 760 void ChangeToRegister(Register Reg, bool isDef, bool isImp = false, 791 static MachineOperand CreateReg(Register Reg, bool isDef, bool isImp = false, 798 assert(!(isDead && !isDef) && "Dead flag on non-def"); 799 assert(!(isKill && isDef) && "Kill flag on def"); 801 Op.IsDef = isDef;
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/ |
H A D | HexagonExpandCondsets.cpp | 375 if (!Op.isReg() || !Op.isDef()) in updateDeadsInRange() 502 if (Op.isDef()) { in updateDeadsInRange() 675 assert(MD.isDef()); in split() 731 if (!Op.isReg() || !Op.isDef()) in isPredicable() 767 if (!Op.isReg() || !Op.isDef()) in getReachingDefForPred() 813 if (Op.isDef() && isRefInMap(RR, Uses, Exec_Then)) in canMoveOver() 880 if (!MO.isReg() || !MO.isDef()) in predicateAt() 928 assert(!Op.isDef() && "Not expecting a def"); in renameInRange() 1007 ReferenceMap &Map = Op.isDef() ? Defs : Uses; in predicate() 1008 if (Op.isDef() && Op.isUndef()) { in predicate()
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/X86/ |
H A D | X86FixupBWInsts.cpp | 263 assert((MO.isDef() || MO.isUse()) && "Expected Def or Use only!"); in getSuperRegDestIfDead() 265 if (MO.isDef() && TRI->isSuperRegisterEq(OrigDestReg, MO.getReg())) in getSuperRegDestIfDead() 339 if (Op.getReg() != (Op.isDef() ? NewDestReg : NewSrcReg)) in tryReplaceCopy()
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
H A D | SIFormMemoryClauses.cpp | 123 if (!MO.isReg() || MO.isDef()) in isValidClauseInst() 170 const RegUse &Map = MO.isDef() ? Uses : Defs; in canBundle() 230 RegUse &Map = MO.isDef() ? Defs : Uses; in collectRegUses()
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