Searched refs:isAssignedRegDep (Results 1 – 10 of 10) sorted by relevance
144 if (S.isAssignedRegDep() && S.getLatency() == 0 && in EmitInstruction()159 if (S.isAssignedRegDep() && S.getLatency() == 0 && in EmitInstruction()
492 if (!I.isAssignedRegDep() || I.getSUnit() != Dst) in restoreLatency()540 if (!I.isAssignedRegDep() || I.getSUnit() != Dst) in changeLatency()556 if (I.isAssignedRegDep() && I.getLatency() == 0 && in getZeroLatency()
707 if (!PI.getSUnit()->getInstr()->isPseudo() && PI.isAssignedRegDep() && in SchedulingCost()716 if (!SI.getSUnit()->getInstr()->isPseudo() && SI.isAssignedRegDep() && in SchedulingCost()
1929 if ((Pred.getLatency() == 0 && Pred.isAssignedRegDep()) || in producesStall()
164 if (Pred.isAssignedRegDep()) { in ReleasePredecessors()193 if (Succ.isAssignedRegDep()) { in ScheduleNodeBottomUp()475 if (Pred.isAssignedRegDep()) { in DelayForLiveRegsBottomUp()
140 assert(!Succ.isAssignedRegDep() && in releaseSuccessors()
558 if (Pred.isAssignedRegDep()) { in ReleasePredecessors()772 if (Succ.isAssignedRegDep() && LiveRegDefs[Succ.getReg()] == SU) { in ScheduleNodeBottomUp()841 if (Pred.isAssignedRegDep() && SU == LiveRegGens[Pred.getReg()]){ in UnscheduleNodeBottomUp()887 if (Succ.isAssignedRegDep()) { in UnscheduleNodeBottomUp()901 if (Succ2.isAssignedRegDep() && Succ2.getReg() == Reg && in UnscheduleNodeBottomUp()1356 if (Pred.isAssignedRegDep() && LiveRegDefs[Pred.getReg()] != SU) in DelayForLiveRegsBottomUp()2853 if (!SuccPred.isAssignedRegDep()) in canClobberReachingPhysRegUse()3034 assert(!Edge.isAssignedRegDep()); in PrescheduleNodesWithMultipleUses()
86 if (TRI && isAssignedRegDep()) in dump()710 if (PredDep.isAssignedRegDep() && in WillCreateCycle()
2727 if (SI.isAssignedRegDep()) in isValidSchedule()
211 bool isAssignedRegDep() const { in isAssignedRegDep() function