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Searched refs:is64BitVector (Results 1 – 9 of 9) sorted by relevance

/netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/
H A DValueTypes.h175 bool is64BitVector() const { in is64BitVector() function
176 return isSimple() ? V.is64BitVector() : isExtended64BitVector(); in is64BitVector()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
H A DARMISelDAGToDAG.cpp336 bool is64BitVector);
1921 unsigned NumVecs, bool is64BitVector) { in GetVLDSTAlign() argument
1923 if (!is64BitVector && NumVecs < 3) in GetVLDSTAlign()
2090 bool is64BitVector = VT.is64BitVector(); in SelectVLD() local
2091 Align = GetVLDSTAlign(Align, dl, NumVecs, is64BitVector); in SelectVLD()
2120 if (!is64BitVector) in SelectVLD()
2136 if (is64BitVector || NumVecs <= 2) { in SelectVLD()
2137 unsigned Opc = (is64BitVector ? DOpcodes[OpcodeIndex] : in SelectVLD()
2205 unsigned Sub0 = (is64BitVector ? ARM::dsub_0 : ARM::qsub_0); in SelectVLD()
2235 bool is64BitVector = VT.is64BitVector(); in SelectVST() local
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H A DARMISelLowering.cpp6227 EVT VT8Bit = VT.is64BitVector() ? MVT::v8i8 : MVT::v16i8; in LowerCTPOP()
6233 unsigned NumElts = VT.is64BitVector() ? 8 : 16; in LowerCTPOP()
7086 if (VT.is64BitVector() && EltSz == 32) in isVUZPMask()
7122 if (VT.is64BitVector() && EltSz == 32) in isVUZP_v_undef_Mask()
7160 if (VT.is64BitVector() && EltSz == 32) in isVZIPMask()
7193 if (VT.is64BitVector() && EltSz == 32) in isVZIP_v_undef_Mask()
7959 (VT.is128BitVector() || VT.is64BitVector())) { in isShuffleMaskLegal()
9035 assert(Op0.getValueType().is64BitVector() && in LowerMUL()
9036 Op1.getValueType().is64BitVector() && in LowerMUL()
11911 if (!N->getValueType(0).is64BitVector()) in AddCombineToVPADD()
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
H A DAArch64CallingConvention.cpp139 else if (LocVT.SimpleTy == MVT::f64 || LocVT.is64BitVector()) in CC_AArch64_Custom_Block()
H A DAArch64ISelLowering.cpp3725 assert(Op0.getValueType().is64BitVector() && in LowerMUL()
3726 Op1.getValueType().is64BitVector() && in LowerMUL()
4744 if (OverrideNEON && (VT.is128BitVector() || VT.is64BitVector())) in useSVEForFixedLengthVectorVT()
4895 else if (RegVT == MVT::f64 || RegVT.is64BitVector()) in LowerFormalArguments()
6847 EVT VT8Bit = VT.is64BitVector() ? MVT::v8i8 : MVT::v16i8; in LowerCTPOP()
6853 unsigned NumElts = VT.is64BitVector() ? 8 : 16; in LowerCTPOP()
8327 if (!SrcVT.is64BitVector()) { in ReconstructShuffle()
10254 (VT.is128BitVector() || VT.is64BitVector())) { in isShuffleMaskLegal()
12612 if (!VT.is64BitVector() && !VT.is128BitVector()) in tryCombineToBSL()
12838 if (!(VT.is64BitVector() || VT.is128BitVector())) in performANDCombine()
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H A DAArch64FastISel.cpp2925 else if ((VT >= MVT::f16 && VT <= MVT::f64) || VT.is64BitVector() || in fastLowerArguments()
2969 } else if ((VT == MVT::f64) || VT.is64BitVector()) { in fastLowerArguments()
H A DAArch64ISelDAGToDAG.cpp1330 } else if (VT == MVT::f64 || VT.is64BitVector()) { in tryIndexedLoad()
/netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/Support/
H A DMachineValueType.h381 bool is64BitVector() const { in is64BitVector() function
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp43724 N0.getOperand(0).getValueType().is64BitVector() && in combineVectorPack()
43729 N1.getOperand(0).getValueType().is64BitVector() && in combineVectorPack()