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Searched refs:input_clk (Results 1 – 5 of 5) sorted by relevance

/netbsd-src/sys/external/bsd/drm2/dist/drm/nouveau/
H A Dnouveau_led.c65 u32 input_clk = 27e6; /* PDISPLAY.SOR[1].PWM is connected to the crystal */ in nouveau_led_set_brightness() local
69 div = input_clk / freq; in nouveau_led_set_brightness()
/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/powerplay/
H A Damdgpu_vega20_ppt.c2609 int32_t input_index, input_clk, input_vol, i; in vega20_odn_edit_dpm_table() local
2635 input_clk = input[i + 1]; in vega20_odn_edit_dpm_table()
2643 if (input_clk < od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMIN].min_value || in vega20_odn_edit_dpm_table()
2644 input_clk > od8_settings->od8_settings_array[OD8_SETTING_GFXCLK_FMAX].max_value) { in vega20_odn_edit_dpm_table()
2646 input_clk, in vega20_odn_edit_dpm_table()
2652 if (input_index == 0 && od_table->GfxclkFmin != input_clk) { in vega20_odn_edit_dpm_table()
2653 od_table->GfxclkFmin = input_clk; in vega20_odn_edit_dpm_table()
2655 } else if (input_index == 1 && od_table->GfxclkFmax != input_clk) { in vega20_odn_edit_dpm_table()
2656 od_table->GfxclkFmax = input_clk; in vega20_odn_edit_dpm_table()
2684 input_clk = input[i + 1]; in vega20_odn_edit_dpm_table()
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/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/powerplay/hwmgr/
H A Damdgpu_vega20_hwmgr.c2925 int32_t input_index, input_clk, input_vol, i; in vega20_odn_edit_dpm_table() local
2948 input_clk = input[i + 1]; in vega20_odn_edit_dpm_table()
2956 if (input_clk < od8_settings[OD8_SETTING_GFXCLK_FMIN].min_value || in vega20_odn_edit_dpm_table()
2957 input_clk > od8_settings[OD8_SETTING_GFXCLK_FMAX].max_value) { in vega20_odn_edit_dpm_table()
2959 input_clk, in vega20_odn_edit_dpm_table()
2965 if ((input_index == 0 && od_table->GfxclkFmin != input_clk) || in vega20_odn_edit_dpm_table()
2966 (input_index == 1 && od_table->GfxclkFmax != input_clk)) in vega20_odn_edit_dpm_table()
2970 od_table->GfxclkFmin = input_clk; in vega20_odn_edit_dpm_table()
2972 od_table->GfxclkFmax = input_clk; in vega20_odn_edit_dpm_table()
2991 input_clk = input[i + 1]; in vega20_odn_edit_dpm_table()
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H A Damdgpu_smu7_hwmgr.c4866 uint32_t input_clk; in smu7_odn_edit_dpm_table() local
4907 input_clk = input[i+1] * 100; in smu7_odn_edit_dpm_table()
4910 if (smu7_check_clk_voltage_valid(hwmgr, type, input_clk, input_vol)) { in smu7_odn_edit_dpm_table()
4911 podn_dpm_table_in_backend->entries[input_level].clock = input_clk; in smu7_odn_edit_dpm_table()
4912 podn_vdd_dep_in_backend->entries[input_level].clk = input_clk; in smu7_odn_edit_dpm_table()
H A Damdgpu_vega10_hwmgr.c5237 uint32_t input_clk; in vega10_odn_edit_dpm_table() local
5280 input_clk = input[i+1] * 100; in vega10_odn_edit_dpm_table()
5283 if (vega10_check_clk_voltage_valid(hwmgr, type, input_clk, input_vol)) { in vega10_odn_edit_dpm_table()
5284 dpm_table->dpm_levels[input_level].value = input_clk; in vega10_odn_edit_dpm_table()
5285 podn_vdd_dep_table->entries[input_level].clk = input_clk; in vega10_odn_edit_dpm_table()