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/netbsd-src/external/gpl3/binutils.old/dist/include/opcode/
H A Dwasm.h57 WASM_OPCODE (0x29, "i64.load", i32, i64, load, agnostic)
64 WASM_OPCODE (0x30, "i64.load8_s", i32, i64, load, signed)
65 WASM_OPCODE (0x31, "i64.load8_u", i32, i64, load, unsigned)
66 WASM_OPCODE (0x32, "i64.load16_s", i32, i64, load, signed)
67 WASM_OPCODE (0x33, "i64.load16_u", i32, i64, load, unsigned)
68 WASM_OPCODE (0x34, "i64.load32_s", i32, i64, load, signed)
69 WASM_OPCODE (0x35, "i64.load32_u", i32, i64, load, unsigned)
71 WASM_OPCODE (0x37, "i64.store", i64, void, store, agnostic)
76 WASM_OPCODE (0x3c, "i64.store8", i64, void, store, agnostic)
77 WASM_OPCODE (0x3d, "i64.store16", i64, void, store, agnostic)
[all …]
/netbsd-src/external/gpl3/binutils/dist/include/opcode/
H A Dwasm.h57 WASM_OPCODE (0x29, "i64.load", i32, i64, load, agnostic)
64 WASM_OPCODE (0x30, "i64.load8_s", i32, i64, load, signed)
65 WASM_OPCODE (0x31, "i64.load8_u", i32, i64, load, unsigned)
66 WASM_OPCODE (0x32, "i64.load16_s", i32, i64, load, signed)
67 WASM_OPCODE (0x33, "i64.load16_u", i32, i64, load, unsigned)
68 WASM_OPCODE (0x34, "i64.load32_s", i32, i64, load, signed)
69 WASM_OPCODE (0x35, "i64.load32_u", i32, i64, load, unsigned)
71 WASM_OPCODE (0x37, "i64.store", i64, void, store, agnostic)
76 WASM_OPCODE (0x3c, "i64.store8", i64, void, store, agnostic)
77 WASM_OPCODE (0x3d, "i64.store16", i64, void, store, agnostic)
[all …]
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Mips/
H A DMips64r6InstrInfo.td208 // i64 selects
209 def : MipsPat<(select i64:$cond, i64:$t, i64:$f),
210 (OR64 (SELNEZ64 i64:$t, i64:$cond),
211 (SELEQZ64 i64:$f, i64:$cond))>,
213 def : MipsPat<(select (i32 (seteq i64:$cond, immz)), i64:$t, i64:$f),
214 (OR64 (SELEQZ64 i64:$t, i64:$cond),
215 (SELNEZ64 i64:$f, i64:$cond))>,
217 def : MipsPat<(select (i32 (setne i64:$cond, immz)), i64:$t, i64:$f),
218 (OR64 (SELNEZ64 i64:$t, i64:$cond),
219 (SELEQZ64 i64:$f, i64:$cond))>,
[all …]
H A DMips64InstrInfo.td23 def immSExt10_64 : PatLeaf<(i64 imm),
26 def immZExt16_64 : PatLeaf<(i64 imm),
29 def immZExt5_64 : ImmLeaf<i64, [{ return Imm == (Imm & 0x1f); }]>;
43 if (N->getValueType(0) == MVT::i64) {
53 if (N->getValueType(0) == MVT::i64) {
645 // Materialize i64 constants.
646 defm : MaterializeImms<i64, ZERO_64, DADDiu, LUi64, ORi64>, ISA_MIPS3, GPR_64;
648 def : MipsPat<(i64 immZExt32Low16Zero:$imm),
651 def : MipsPat<(i64 immZExt32:$imm),
656 def : MipsPat<(i64 (extloadi1 addr:$src)), (LB64 addr:$src)>, ISA_MIPS3,
[all …]
H A DMipsCallingConv.td55 // pair of i64's.
71 CCIfType<[i64], CCDelegateTo<RetCC_F128SoftFloat>>>,
73 CCIfType<[i64], CCDelegateTo<RetCC_F128HardFloat>>>
134 CCIfType<[i8, i16, i32, i64],
136 CCIfInReg<CCPromoteToUpperBitsInType<i64>>>>,
139 CCIfType<[i8, i16, i32], CCIfOrigArgWasNotFloat<CCPromoteToType<i64>>>,
146 CCIfType<[i64], CCAssignToRegWithShadow<[A0_64, A1_64, A2_64, A3_64,
165 CCIfType<[i64, f64], CCAssignToStack<8, 8>>
171 CCIfType<[i8, i16, i32, i64],
173 CCIfInReg<CCPromoteToUpperBitsInType<i64>>>>,
[all …]
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Sparc/
H A DSparcInstr64Bit.td18 // The same integer registers are used for i32 and i64 values.
21 def : Pat<(i64 (anyext i32:$val)), (COPY_TO_REGCLASS $val, I64Regs)>;
22 def : Pat<(i32 (trunc i64:$val)), (COPY_TO_REGCLASS $val, IntRegs)>;
39 def : Pat<(i64 (zext i32:$val)), (SRLri $val, 0)>;
40 def : Pat<(i64 (sext i32:$val)), (SRAri $val, 0)>;
42 def : Pat<(i64 (and i64:$val, 0xffffffff)), (SRLri $val, 0)>;
43 def : Pat<(i64 (sext_inreg i64:$val, i32)), (SRAri $val, 0)>;
45 defm SLLX : F3_S<"sllx", 0b100101, 1, shl, i64, shift_imm6, I64Regs>;
46 defm SRLX : F3_S<"srlx", 0b100110, 1, srl, i64, shift_imm6, I64Regs>;
47 defm SRAX : F3_S<"srax", 0b100111, 1, sra, i64, shift_imm6, I64Regs>;
[all …]
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/VE/
H A DVEInstrIntrinsicVL.gen.td1 def : Pat<(int_ve_vl_vld_vssl i64:$sy, i64:$sz, i32:$vl), (VLDrrl i64:$sy, i64:$sz, i32:$vl)>;
2 def : Pat<(int_ve_vl_vld_vssvl i64:$sy, i64:$sz, v256f64:$pt, i32:$vl), (VLDrrl_v i64:$sy, i64:$sz,…
3 def : Pat<(int_ve_vl_vld_vssl simm7:$I, i64:$sz, i32:$vl), (VLDirl (LO7 $I), i64:$sz, i32:$vl)>;
4 def : Pat<(int_ve_vl_vld_vssvl simm7:$I, i64:$sz, v256f64:$pt, i32:$vl), (VLDirl_v (LO7 $I), i64:$s…
5 def : Pat<(int_ve_vl_vldnc_vssl i64:$sy, i64:$sz, i32:$vl), (VLDNCrrl i64:$sy, i64:$sz, i32:$vl)>;
6 def : Pat<(int_ve_vl_vldnc_vssvl i64:$sy, i64:$sz, v256f64:$pt, i32:$vl), (VLDNCrrl_v i64:$sy, i64:…
7 def : Pat<(int_ve_vl_vldnc_vssl simm7:$I, i64:$sz, i32:$vl), (VLDNCirl (LO7 $I), i64:$sz, i32:$vl)>;
8 def : Pat<(int_ve_vl_vldnc_vssvl simm7:$I, i64:$sz, v256f64:$pt, i32:$vl), (VLDNCirl_v (LO7 $I), i6…
9 def : Pat<(int_ve_vl_vldu_vssl i64:$sy, i64:$sz, i32:$vl), (VLDUrrl i64:$sy, i64:$sz, i32:$vl)>;
10 def : Pat<(int_ve_vl_vldu_vssvl i64:$sy, i64:$sz, v256f64:$pt, i32:$vl), (VLDUrrl_v i64:$sy, i64:$s…
[all …]
H A DVEInstrInfo.td429 def SDT_SPCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i64>,
430 SDTCisVT<1, i64> ]>;
431 def SDT_SPCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i64>,
432 SDTCisVT<1, i64> ]>;
439 def SDT_SPCall : SDTypeProfile<0, -1, [SDTCisVT<0, i64>]>;
1007 defm LD : LOADm<"ld", 0x01, I64, i64, load>;
1065 defm ST : STOREm<"st", 0x11, I64, i64, store>;
1096 defm DLD : LOADm<"dld", 0x09, I64, i64, load>;
1114 defm TS1AML : RRCASm<"ts1am.l", 0x42, I64, i64, uimm7>;
1120 defm TS2AM : RRCASm<"ts2am", 0x43, I64, i64, uimm7>;
[all …]
H A DVECallingConv.td31 // Promote i1/i8/i16/i32 arguments to i64.
32 CCIfType<[i1, i8, i16, i32], CCPromoteToType<i64>>,
34 // Convert float arguments to i64 with padding.
39 CCIfType<[f32], CCBitConvertToType<i64>>,
43 CCIfType<[i64, f64],
62 // Promote i1/i8/i16/i32 arguments to i64.
63 CCIfType<[i1, i8, i16, i32], CCPromoteToType<i64>>,
65 // Convert float arguments to i64 with padding.
70 CCIfType<[f32], CCBitConvertToType<i64>>,
79 // Promote i1/i8/i16/i32 return values to i64.
[all …]
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/WebAssembly/
H A DWebAssemblyInstrAtomics.td141 defm : WaitPatNoOffset<i64, int_wasm_memory_atomic_wait64,
145 defm : WaitPatNoOffset<i64, int_wasm_memory_atomic_wait64,
166 defm : WaitPatImmOff<i64, int_wasm_memory_atomic_wait64, regPlusImm,
168 defm : WaitPatImmOff<i64, int_wasm_memory_atomic_wait64, or_is_add,
184 defm : WaitPatOffsetOnly<i64, int_wasm_memory_atomic_wait64,
201 defm : WaitPatGlobalAddrOffOnly<i64, int_wasm_memory_atomic_wait64,
227 defm ATOMIC_LOAD_I64 : AtomicLoad<I64, "i64.atomic.load", 0x11>;
231 defm : LoadPatNoOffset<i64, atomic_load_64, "ATOMIC_LOAD_I64">;
237 defm : LoadPatImmOff<i64, atomic_load_64, regPlusImm, "ATOMIC_LOAD_I64">;
239 defm : LoadPatImmOff<i64, atomic_load_64, or_is_add, "ATOMIC_LOAD_I64">;
[all …]
H A DWebAssemblyInstrMemory.td18 // WebAssembly has i8/i16/i32/i64/f32/f64 memory types, but doesn't have i8/i16
65 defm LOAD_I64 : WebAssemblyLoad<I64, "i64.load", 0x29, []>;
73 def : Pat<(ty (kind (i64 I64:$addr))), (!cast<NI>(inst # "_A64") 0, 0, I64:$addr)>,
78 defm : LoadPatNoOffset<i64, load, "LOAD_I64">;
96 defm : LoadPatImmOff<i64, load, regPlusImm, "LOAD_I64">;
100 defm : LoadPatImmOff<i64, load, or_is_add, "LOAD_I64">;
115 defm : LoadPatOffsetOnly<i64, load, "LOAD_I64">;
129 defm : LoadPatGlobalAddrOffOnly<i64, load, "LOAD_I64">;
138 defm LOAD8_S_I64 : WebAssemblyLoad<I64, "i64.load8_s", 0x30, []>;
139 defm LOAD8_U_I64 : WebAssemblyLoad<I64, "i64.load8_u", 0x31, []>;
[all …]
H A DWebAssemblyInstrConv.td21 "i64.extend_i32_s\t$dst, $src", "i64.extend_i32_s",
25 "i64.extend_i32_u\t$dst, $src", "i64.extend_i32_u",
39 "i64.extend8_s\t$dst, $src", "i64.extend8_s",
43 "i64.extend16_s\t$dst, $src", "i64.extend16_s",
47 "i64.extend32_s\t$dst, $src", "i64.extend32_s",
54 def : Pat<(i64 (anyext I32:$src)), (I64_EXTEND_U_I32 I32:$src)>;
70 "i64.trunc_sat_f32_s\t$dst, $src",
71 "i64.trunc_sat_f32_s", 0xfc04>,
75 "i64.trunc_sat_f32_u\t$dst, $src",
76 "i64.trunc_sat_f32_u", 0xfc05>,
[all …]
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/
H A DPPCInstr64Bit.td17 def s16imm64 : Operand<i64> {
24 def u16imm64 : Operand<i64> {
31 def s17imm64 : Operand<i64> {
44 def tlsreg : Operand<i64> {
48 def tlsgd : Operand<i64> {}
49 def tlscall : Operand<i64> {
131 "bla $func", IIC_BrB, [(PPCcall (i64 imm:$func))]>;
145 [(PPCcall_nop (i64 imm:$func))]>;
202 def : Pat<(PPCcall (i64 tglobaladdr:$dst)),
204 def : Pat<(PPCcall_nop (i64 tglobaladdr:$dst)),
[all …]
H A DPPCISelDAGToDAG.cpp187 return CurDAG->getTargetConstant(Imm, dl, MVT::i64); in getI64Imm()
555 if (N->getOpcode() == ISD::Constant && N->getValueType(0) == MVT::i64) { in isInt64Immediate()
718 case MVT::i64: { in tryTLSXFormStore()
762 case MVT::i64: { in tryTLSXFormLoad()
938 SDValue SDImm = CurDAG->getTargetConstant(Imm, dl, MVT::i64); in selectI64ImmDirect()
939 return CurDAG->getMachineNode(PPC::LI8, dl, MVT::i64, SDImm); in selectI64ImmDirect()
944 return CurDAG->getMachineNode(PPC::LIS8, dl, MVT::i64, in selectI64ImmDirect()
957 Result = CurDAG->getMachineNode(Opcode, dl, MVT::i64, getI32Imm(ImmHi16)); in selectI64ImmDirect()
958 return CurDAG->getMachineNode(PPC::ORI8, dl, MVT::i64, SDValue(Result, 0), in selectI64ImmDirect()
968 Result = CurDAG->getMachineNode(PPC::LI8, dl, MVT::i64, in selectI64ImmDirect()
[all …]
H A DPPCInstrVSX.td1303 [(set i64:$rA, (PPCmfvsr f64:$XT))]>,
1321 [(set f64:$XT, (PPCmtvsra i64:$rA))]>,
1699 [(set v4i32:$XT, (int_ppc_vsx_lxvl addr:$src, i64:$rB))]>;
1702 [(set v4i32:$XT, (int_ppc_vsx_lxvll addr:$src, i64:$rB))]>;
1744 i64:$rB)]>;
1749 i64:$rB)]>;
1817 // Output dag used to bitcast f32 to i32 and f64 to i64
1821 dag DblToLong = (i64 (MFVSRD $A));
1836 dag ZELi8i64 = (i64 (zextloadi8 ForceXForm:$src));
1838 dag SELi8i64 = (i64 (sext_inreg (extloadi8 ForceXForm:$src), i8));
[all …]
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/BPF/
H A DBPFInstrInfo.td30 def SDT_BPFMEMCPY : SDTypeProfile<0, 4, [SDTCisVT<0, i64>,
31 SDTCisVT<1, i64>,
32 SDTCisVT<2, i64>,
33 SDTCisVT<3, i64>]>;
60 def calltarget : Operand<i64>;
62 def u64imm : Operand<i64> {
66 def i64immSExt32 : PatLeaf<(i64 imm),
72 def ADDRri : ComplexPattern<i64, 2, "SelectAddr", [], []>;
73 def FIri : ComplexPattern<i64, 2, "SelectFIAddr", [add, or], []>;
76 def MEMri : Operand<i64> {
[all …]
H A DBPFCallingConv.td14 def RetCC_BPF64 : CallingConv<[CCIfType<[i64], CCAssignToReg<[R0]>>]>;
18 // Promote i8/i16/i32 args to i64
19 CCIfType<[ i8, i16, i32 ], CCPromoteToType<i64>>,
22 CCIfType<[i64], CCAssignToReg<[ R1, R2, R3, R4, R5 ]>>,
31 CCIfType<[i64], CCAssignToRegWithShadow<[R0], [W0]>>
36 // Promote i8/i16/i32 args to i64
41 CCIfType<[i64], CCAssignToRegWithShadow<[R1, R2, R3, R4, R5],
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/SystemZ/
H A DSystemZOperands.td172 // These all create MVT::i64 nodes to ensure the value is not sign-extended
179 return CurDAG->getTargetConstant(Value, SDLoc(N), MVT::i64);
185 return CurDAG->getTargetConstant(Value, SDLoc(N), MVT::i64);
191 return CurDAG->getTargetConstant(Value, SDLoc(N), MVT::i64);
197 return CurDAG->getTargetConstant(Value, SDLoc(N), MVT::i64);
203 return CurDAG->getTargetConstant(Value, SDLoc(N), MVT::i64);
209 return CurDAG->getTargetConstant(Value, SDLoc(N), MVT::i64);
215 return CurDAG->getTargetConstant(Value, SDLoc(N), MVT::i64);
220 return CurDAG->getTargetConstant(Value, SDLoc(N), MVT::i64);
226 MVT::i64);
[all …]
H A DSystemZCallingConv.td36 // Promote i32 to i64 if it has an explicit extension type.
37 CCIfType<[i32], CCIfExtend<CCPromoteToType<i64>>>,
40 CCIfSwiftError<CCIfType<[i64], CCAssignToReg<[R9D]>>>,
47 CCIfType<[i64], CCAssignToReg<[R2D, R3D, R4D, R5D]>>,
69 CCIfType<[i64], CCAssignToReg<[R7D, R8D, R10D, R11D, R12D, R13D,
93 // Promote i32 to i64 if it has an explicit extension type.
97 CCIfType<[i32], CCIfExtend<CCPromoteToType<i64>>>,
100 CCIfSwiftSelf<CCIfType<[i64], CCAssignToReg<[R10D]>>>,
103 CCIfSwiftError<CCIfType<[i64], CCAssignToReg<[R9D]>>>,
105 // Force long double values to the stack and pass i64 pointers to them.
[all …]
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Analysis/
H A DREADME.txt13 …(-2 + (2 * (trunc i65 (((zext i64 (-2 + %n) to i65) * (zext i64 (-1 + %n) to i65)) /u 2) to i64)) …
24 ((trunc i64 (-1 * %arg5) to i32) + (trunc i64 %arg5 to i32) + (-1 * (trunc i64 undef to i32)))
28 (-1 * (trunc i64 undef to i32))
/netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/IR/
H A DIntrinsicsVEVL.gen.td1 …ltin<"__builtin_ve_vl_vld_vssl">, Intrinsic<[LLVMType<v256f64>], [LLVMType<i64>, llvm_ptr_ty, LLVM…
2 …tin<"__builtin_ve_vl_vld_vssvl">, Intrinsic<[LLVMType<v256f64>], [LLVMType<i64>, llvm_ptr_ty, LLVM…
3 …in<"__builtin_ve_vl_vldnc_vssl">, Intrinsic<[LLVMType<v256f64>], [LLVMType<i64>, llvm_ptr_ty, LLVM…
4 …n<"__builtin_ve_vl_vldnc_vssvl">, Intrinsic<[LLVMType<v256f64>], [LLVMType<i64>, llvm_ptr_ty, LLVM…
5 …tin<"__builtin_ve_vl_vldu_vssl">, Intrinsic<[LLVMType<v256f64>], [LLVMType<i64>, llvm_ptr_ty, LLVM…
6 …in<"__builtin_ve_vl_vldu_vssvl">, Intrinsic<[LLVMType<v256f64>], [LLVMType<i64>, llvm_ptr_ty, LLVM…
7 …n<"__builtin_ve_vl_vldunc_vssl">, Intrinsic<[LLVMType<v256f64>], [LLVMType<i64>, llvm_ptr_ty, LLVM…
8 …<"__builtin_ve_vl_vldunc_vssvl">, Intrinsic<[LLVMType<v256f64>], [LLVMType<i64>, llvm_ptr_ty, LLVM…
9 …n<"__builtin_ve_vl_vldlsx_vssl">, Intrinsic<[LLVMType<v256f64>], [LLVMType<i64>, llvm_ptr_ty, LLVM…
10 …<"__builtin_ve_vl_vldlsx_vssvl">, Intrinsic<[LLVMType<v256f64>], [LLVMType<i64>, llvm_ptr_ty, LLVM…
[all …]
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
H A DAArch64CallingConvention.td27 CCIfType<[iPTR], CCBitConvertToType<i64>>,
52 CCIfInReg<CCIfType<[i64],
53 CCIfSRet<CCIfType<[i64], CCAssignToRegWithShadow<[X0, X1], [W0, W1]>>>>>,
55 CCIfSRet<CCIfType<[i64], CCAssignToRegWithShadow<[X8], [W8]>>>,
67 CCIfSwiftSelf<CCIfType<[i64], CCAssignToRegWithShadow<[X20], [W20]>>>,
70 CCIfSwiftError<CCIfType<[i64], CCAssignToRegWithShadow<[X21], [W21]>>>,
74 CCIfSwiftAsync<CCIfType<[i64], CCAssignToRegWithShadow<[X22], [W22]>>>,
83 CCPassIndirect<i64>>,
88 CCPassIndirect<i64>>,
90 // Handle i1, i8, i16, i32, i64, f32, f64 and v2f64 by passing in registers,
[all …]
H A DAArch64InstrInfo.td274 def SDT_AArch64ldp : SDTypeProfile<2, 1, [SDTCisVT<0, i64>, SDTCisSameAs<0, 1>, SDTCisPtrTy<2>]>;
275 def SDT_AArch64stp : SDTypeProfile<0, 3, [SDTCisVT<0, i64>, SDTCisSameAs<0, 1>, SDTCisPtrTy<2>]>;
291 [SDTCisVT<0, i64>, SDTCisVT<1, i32>,
612 SDTypeProfile<1, 1, [SDTCisVT<0, i64>, SDTCisVT<1, i32>]>,
872 (i64 0))))),
970 def : Pat<(v2i64 (int_aarch64_crypto_xar (v2i64 V128:$Vn), (v2i64 V128:$Vm), (i64 timm0_63:$imm))),
995 …: Pat<(v4i32 (OpNode (v4i32 V128:$Vd), (v4i32 V128:$Vn), (v4i32 V128:$Vm), (i64 VectorIndexS_timm:…
1299 def : Pat<(i64 (int_aarch64_get_fpcr)), (MRS 0xda20)>;
1300 def : Pat<(int_aarch64_set_fpcr i64:$val), (MSR 0xda20, GPR64:$val)>;
1423 def i64imm_32bit : ImmLeaf<i64, [{
[all …]
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
H A DFLATInstructions.td9 def FlatOffset : ComplexPattern<i64, 2, "SelectFlatOffset", [], [SDNPWantRoot], -10>;
10 def GlobalOffset : ComplexPattern<i64, 2, "SelectGlobalOffset", [], [SDNPWantRoot], -10>;
13 def GlobalSAddr : ComplexPattern<i64, 3, "SelectGlobalSAddr", [], [SDNPWantRoot], -10>;
395 (atomic (FlatOffset i64:$vaddr, i16:$offset), data_vt:$vdata))]>,
453 (atomic (GlobalOffset i64:$vaddr, i16:$offset), data_vt:$vdata))]>,
524 VReg_64, i64, AMDGPUatomic_cmp_swap_flat_64,
531 VReg_64, i64, atomic_swap_flat_64>;
567 VReg_64, i64, atomic_load_add_flat_64>;
570 VReg_64, i64, atomic_load_sub_flat_64>;
573 VReg_64, i64, atomic_load_min_flat_64>;
[all …]
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/
H A DHexagonCallingConv.td17 CCIfType<[i64,v2i32,v4i16,v8i8],
27 CCBitConvertToType<i64>>,
43 CCIfType<[i64,v2i32,v4i16,v8i8],
45 CCIfType<[i64,v2i32,v4i16,v8i8],
57 CCBitConvertToType<i64>>,
73 CCIfType<[i64,v2i32,v4i16,v8i8],
75 CCIfType<[i64,v2i32,v4i16,v8i8],
87 CCBitConvertToType<i64>>,
99 CCIfType<[i64,v2i32,v4i16,v8i8],

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