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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AVR/
H A DAVRInstrInfo.td19 def SDT_AVRCallSeqStart : SDCallSeqStart<[SDTCisVT<0, i16>, SDTCisVT<1, i16>]>;
20 def SDT_AVRCallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i16>, SDTCisVT<1, i16>]>;
94 return CurDAG->getTargetConstant(-N->getAPIntValue(), SDLoc(N), MVT::i16);
213 def imm16 : Operand<i16>
219 def imm_arith6 : Operand<i16>
258 def LDSTPtrReg : Operand<i16>
269 def LDDSTDPtrReg : Operand<i16>
404 [(set i16:$rd, (add i16:$src, i16:$rr)),
429 [(set i16:$rd, (adde i16:$src, i16:$rr)),
438 [(set i16:$rd, (add i16:$src, uimm6:$k)),
[all …]
H A DAVRISelLowering.cpp40 addRegisterClass(MVT::i16, &AVR::DREGSRegClass); in AVRTargetLowering()
51 setOperationAction(ISD::GlobalAddress, MVT::i16, Custom); in AVRTargetLowering()
52 setOperationAction(ISD::BlockAddress, MVT::i16, Custom); in AVRTargetLowering()
57 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i16, Expand); in AVRTargetLowering()
66 setTruncStoreAction(MVT::i16, MVT::i8, Expand); in AVRTargetLowering()
85 setOperationAction(ISD::SRA, MVT::i16, Custom); in AVRTargetLowering()
86 setOperationAction(ISD::SHL, MVT::i16, Custom); in AVRTargetLowering()
87 setOperationAction(ISD::SRL, MVT::i16, Custom); in AVRTargetLowering()
88 setOperationAction(ISD::SHL_PARTS, MVT::i16, Expand); in AVRTargetLowering()
89 setOperationAction(ISD::SRA_PARTS, MVT::i16, Expand); in AVRTargetLowering()
[all …]
H A DAVRISelDAGToDAG.cpp100 Disp = CurDAG->getTargetConstant(RHSC, dl, MVT::i16); in SelectAddr()
110 if (isUInt<6>(RHSC) && (VT == MVT::i8 || VT == MVT::i16)) { in SelectAddr()
147 case MVT::i16: { in selectIndexedLoad()
188 case MVT::i16: { in selectIndexedProgMemLoad()
316 CurDAG->getTargetConstant(0, SDLoc(N), MVT::i16)); in select()
342 SDValue Offset = CurDAG->getTargetConstant(CST, DL, MVT::i16); in select()
344 unsigned Opc = (VT == MVT::i16) ? AVR::STDWSPQRr : AVR::STDSPQRr; in select()
375 Ptr = CurDAG->getCopyFromReg(Chain, DL, AVR::R31R30, MVT::i16, in select()
378 SDValue RegZ = CurDAG->getRegister(AVR::R31R30, MVT::i16); in select()
383 ResNode = CurDAG->getMachineNode(LPMOpc, DL, VT, MVT::i16, MVT::Other, Ptr, in select()
[all …]
H A DAVRRegisterInfo.td107 // Pseudo registers for unaligned i16
159 def DREGS : RegisterClass<"AVR", [i16], 8,
175 def DREGSMOVW : RegisterClass<"AVR", [i16], 8,
195 def DREGS_WITHOUT_YZ_WORKAROUND : RegisterClass<"AVR", [i16], 8,
207 def DLDREGS : RegisterClass<"AVR", [i16], 8,
218 def IWREGS : RegisterClass<"AVR", [i16], 8,
230 def PTRREGS : RegisterClass<"AVR", [i16], 8,
239 def PTRDISPREGS : RegisterClass<"AVR", [i16], 8,
246 def ZREG : RegisterClass<"AVR", [i16], 8, (add R31R30)>;
249 def GPRSP: RegisterClass<"AVR", [i16], 8, (add SP)>;
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/M68k/
H A DM68kExpandPseudo.cpp85 return TII->ExpandMOVX_RR(MIB, MVT::i16, MVT::i8); in ExpandMI()
89 return TII->ExpandMOVX_RR(MIB, MVT::i32, MVT::i16); in ExpandMI()
92 return TII->ExpandMOVSZX_RR(MIB, true, MVT::i16, MVT::i8); in ExpandMI()
96 return TII->ExpandMOVSZX_RR(MIB, true, MVT::i32, MVT::i16); in ExpandMI()
99 return TII->ExpandMOVSZX_RR(MIB, false, MVT::i16, MVT::i8); in ExpandMI()
103 return TII->ExpandMOVSZX_RR(MIB, false, MVT::i32, MVT::i16); in ExpandMI()
106 return TII->ExpandMOVSZX_RM(MIB, true, TII->get(M68k::MOV8dj), MVT::i16, in ExpandMI()
113 MVT::i16); in ExpandMI()
116 return TII->ExpandMOVSZX_RM(MIB, false, TII->get(M68k::MOV8dj), MVT::i16, in ExpandMI()
123 MVT::i16); in ExpandMI()
[all …]
H A DM68kInstrArithmetic.td490 def : Pat<(sext_inreg i16:$src, i8), (EXT16 $src)>;
491 def : Pat<(sext_inreg i32:$src, i16), (EXT32 $src)>;
551 return CurDAG->getTargetConstant(N->getSExtValue(), SDLoc(N), MVT::i16);
575 // RR i16
576 def : Pat<(sdiv i16:$dst, i16:$opd),
581 def : Pat<(udiv i16:$dst, i16:$opd),
586 def : Pat<(srem i16:$dst, i16:$opd),
591 def : Pat<(urem i16:$dst, i16:$opd),
618 // RI i16
619 def : Pat<(sdiv i16:$dst, MximmSExt16:$opd),
[all …]
H A DM68kRegisterInfo.td90 def DR16 : MxRegClass<[i16], 16, (sequence "WD%u", 0, 7)>;
94 def AR16 : MxRegClass<[i16], 16, (add (sequence "WA%u", 0, 6), WSP)>;
101 def XR16 : MxRegClass<[i16], 16, (add DR16, AR16)>;
108 def SRC : MxRegClass<[i16], 16, (add SR)>;
116 def DR16_TC : MxRegClass<[i16], 16, (add D0, D1)>;
119 def AR16_TC : MxRegClass<[i16], 16, (add A0, A1)>;
122 def XR16_TC : MxRegClass<[i16], 16, (add DR16_TC, AR16_TC)>;
H A DM68kCallingConv.td34 CCIfType<[i16], CCAssignToReg<[WD0, WD1]>>,
46 CCIfType<[i16], CCAssignToReg<[WD0, WD1, WA0, WA1]>>,
73 /// Promote i1/i8/i16 arguments to i32.
74 CCIfType<[i1, i8, i16], CCPromoteToType<i32>>,
88 /// Promote i1/i8/i16 arguments to i32.
89 CCIfType<[i1, i8, i16], CCPromoteToType<i32>>,
H A DM68kInstrInfo.td195 def MxXRD16 : MxRegOp<i16, XR16, MxSize16, "r">;
198 def MxXRD16_TC : MxRegOp<i16, XR16_TC, MxSize16, "r">;
204 def MxDRD16 : MxRegOp<i16, DR16, MxSize16, "d">;
207 def MxDRD16_TC : MxRegOp<i16, DR16_TC, MxSize16, "d">;
212 def MxARD16 : MxRegOp<i16, AR16, MxSize16, "a">;
215 def MxARD16_TC : MxRegOp<i16, AR16_TC, MxSize16, "a">;
369 def Mxi16imm : MxOp<i16, MxSize16, "i">;
385 def MxMoveMask : MxOp<i16, MxSize16, "m"> {
473 def MximmSExt16 : PatLeaf<(i16 imm)>;
483 def Mximm16_1to8 : ImmLeaf<i16, [{ return Imm >= 1 && Imm <= 8; }]>;
[all …]
/netbsd-src/external/apache2/llvm/dist/clang/docs/
H A DDataFlowSanitizerDesign.rst177 define linkonce_odr { i8*, i16 } @"dfsw$malloc"(i64 %0, i16 %1) {
180 %3 = insertvalue { i8*, i16 } undef, i8* %2, 0
181 %4 = insertvalue { i8*, i16 } %3, i16 0, 1
182 ret { i8*, i16 } %4
185 define linkonce_odr { i32, i16 } @"dfsw$tolower"(i32 %0, i16 %1) {
188 %3 = insertvalue { i32, i16 } undef, i32 %2, 0
189 %4 = insertvalue { i32, i16 } %3, i16 %1, 1
190 ret { i32, i16 } %4
193 … define linkonce_odr { i8*, i16 } @"dfsw$memcpy"(i8* %0, i8* %1, i64 %2, i16 %3, i16 %4, i16 %5) {
195 %labelreturn = alloca i16
[all …]
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/MSP430/
H A DMSP430ISelDAGToDAG.cpp253 AM.Base.Reg = CurDAG->getRegister(MSP430::SR, MVT::i16); in SelectAddr()
263 MVT::i16, AM.Disp, in SelectAddr()
266 Disp = CurDAG->getTargetConstantPool(AM.CP, MVT::i16, AM.Alignment, AM.Disp, in SelectAddr()
269 Disp = CurDAG->getTargetExternalSymbol(AM.ES, MVT::i16, 0/*AM.SymbolFlags*/); in SelectAddr()
271 Disp = CurDAG->getTargetJumpTable(AM.JT, MVT::i16, 0/*AM.SymbolFlags*/); in SelectAddr()
276 Disp = CurDAG->getTargetConstant(AM.Disp, SDLoc(N), MVT::i16); in SelectAddr()
312 case MVT::i16: in isValidIndexedLoad()
337 case MVT::i16: in tryIndexedLoad()
345 CurDAG->getMachineNode(Opcode, SDLoc(N), VT, MVT::i16, MVT::Other, in tryIndexedLoad()
360 unsigned Opc = (VT == MVT::i16 ? Opc16 : Opc8); in tryIndexedBinOp()
[all …]
H A DMSP430ISelLowering.cpp50 addRegisterClass(MVT::i16, &MSP430::GR16RegClass); in MSP430TargetLowering()
62 setIndexedLoadAction(ISD::POST_INC, MVT::i16, Legal); in MSP430TargetLowering()
69 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i16, Expand); in MSP430TargetLowering()
73 setTruncStoreAction(MVT::i16, MVT::i8, Expand); in MSP430TargetLowering()
78 setOperationAction(ISD::SRA, MVT::i16, Custom); in MSP430TargetLowering()
79 setOperationAction(ISD::SHL, MVT::i16, Custom); in MSP430TargetLowering()
80 setOperationAction(ISD::SRL, MVT::i16, Custom); in MSP430TargetLowering()
83 setOperationAction(ISD::ROTL, MVT::i16, Expand); in MSP430TargetLowering()
84 setOperationAction(ISD::ROTR, MVT::i16, Expand); in MSP430TargetLowering()
85 setOperationAction(ISD::GlobalAddress, MVT::i16, Custom); in MSP430TargetLowering()
[all …]
H A DMSP430CallingConv.td18 // i16 are returned in registers R12, R13, R14, R15
19 CCIfType<[i16], CCAssignToReg<[R12, R13, R14, R15]>>
29 // Promote i8 arguments to i16.
30 CCIfType<[i8], CCPromoteToType<i16>>,
34 CCIfType<[i16], CCAssignToStack<2, 2>>
H A DMSP430InstrInfo.td19 class SDTCisI16<int OpNum> : SDTCisVT<OpNum, i16>;
25 def SDT_MSP430CallSeqStart : SDCallSeqStart<[SDTCisVT<0, i16>,
26 SDTCisVT<1, i16>]>;
27 def SDT_MSP430CallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i16>, SDTCisVT<1, i16>]>;
78 def memsrc : Operand<i16> {
86 def memdst : Operand<i16> {
99 def indreg : Operand<i16> {
111 def postreg : Operand<i16> {
143 def cg16imm : Operand<i16>,
144 ImmLeaf<i16, [{return Imm == 0 || Imm == 1 || Imm == 2 ||
[all …]
/netbsd-src/external/lgpl3/gmp/dist/mpn/sparc64/ultrasparc1234/
H A Dmul_1.asm57 C the i00,i16,i32,i48 RAW less apart. The latter apart-scheduling should
59 C that i16 needs to be copied.
92 define(`i00',`%l0') define(`i16',`%l1') define(`i32',`%l2') define(`i48',`%l3')
171 ldx [%sp+2223+8], i16
180 srlx i16, 48, %l4 C (i16 >> 48)
181 mov i16, %g2
182 ldx [%sp+2223+8], i16
237 ldx [%sp+2223+8], i16
251 srlx i16, 48, %l4 C (i16 >> 48)
252 mov i16, %g2
[all …]
H A Daddmul_1.asm58 C the i00,i16,i32,i48 RAW less apart. The latter apart-scheduling should
60 C that i16 needs to be copied.
93 define(`i00',`%l0') define(`i16',`%l1') define(`i32',`%l2') define(`i48',`%l3')
173 ldx [%sp+2223+8], i16
184 srlx i16, 48, %l4 C (i16 >> 48)
185 mov i16, %g2
186 ldx [%sp+2223+8], i16
242 ldx [%sp+2223+8], i16
259 srlx i16, 48, %l4 C (i16 >> 48)
260 mov i16, %g2
[all …]
/netbsd-src/external/apache2/llvm/dist/llvm/docs/
H A DExtendedIntegerResults.txt13 the front-end is referencing (typically i1/i8/i16/i32).
63 %0 = tail call signext i16 (...)* @y() nounwind
64 %1 = sext i16 %0 to i32
70 define signext i16 @b() nounwind {
73 %retval12 = trunc i32 %0 to i16 ; <i16> [#uses=1]
74 ret i16 %retval12
97 %1 = trunc i32 %0 to i16
98 %2 = sext i16 %1 to i32
104 %retval12 = trunc i32 %0 to i16
105 %tmp = sext i16 %retval12 to i32
[all …]
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
H A DAMDGPUCallingConv.td23 CCIfInReg<CCIfType<[f32, i32, f16, i16, v2i16, v2f16] , CCAssignToReg<[
30 CCIfNotInReg<CCIfType<[f32, i32, f16, i16, v2i16, v2f16] , CCAssignToReg<[
37 CCIfType<[i32, f32, v2i16, v2f16, i16, f16, i1], CCAssignToStack<4, 4>>
42 CCIfType<[i1, i16], CCIfExtend<CCPromoteToType<i32>>>,
46 CCIfInReg<CCIfType<[f32, i32, f16, i16, v2i16, v2f16] , CCAssignToReg<[
55 CCIfNotInReg<CCIfType<[f32, i32, f16, i16, v2i16, v2f16] , CCAssignToReg<[
78 CCIfInReg<CCIfType<[f32, i32, f16, i16, v2i16, v2f16] , CCAssignToReg<[
88 CCIfNotInReg<CCIfType<[f32, i32, f16, i16, v2i16, v2f16] , CCAssignToReg<[
110 CCIfType<[i32, i16] , CCAssignToReg<[
206 CCIfType<[i8, i16], CCIfExtend<CCPromoteToType<i32>>>,
[all …]
H A DFLATInstructions.td395 (atomic (FlatOffset i64:$vaddr, i16:$offset), data_vt:$vdata))]>,
453 (atomic (GlobalOffset i64:$vaddr, i16:$offset), data_vt:$vdata))]>,
820 (vt (node (FlatOffset i64:$vaddr, i16:$offset))),
825 (node (FlatOffset (i64 VReg_64:$vaddr), i16:$offset), vt:$in),
830 (node (GlobalOffset (i64 VReg_64:$vaddr), i16:$offset), vt:$in),
835 (vt (node (GlobalSAddr (i64 SReg_64:$saddr), (i32 VGPR_32:$voffset), i16:$offset), vt:$in)),
840 (vt (node (GlobalOffset (i64 VReg_64:$vaddr), i16:$offset))),
845 (vt (node (GlobalSAddr (i64 SReg_64:$saddr), (i32 VGPR_32:$voffset), i16:$offset))),
851 (node vt:$data, (GlobalSAddr (i64 SReg_64:$saddr), (i32 VGPR_32:$voffset), i16:$offset)),
857 (node (GlobalSAddr (i64 SReg_64:$saddr), (i32 VGPR_32:$voffset), i16:$offset), vt:$data),
[all …]
/netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/
H A DValueTypes.td24 def i16 : ValueType<16, 4>; // 16-bit integer value
59 def v1i16 : ValueType<16, 35>; // 1 x i16 vector value
60 def v2i16 : ValueType<32, 36>; // 2 x i16 vector value
61 def v3i16 : ValueType<48, 37>; // 3 x i16 vector value
62 def v4i16 : ValueType<64, 38>; // 4 x i16 vector value
63 def v8i16 : ValueType<128, 39>; // 8 x i16 vector value
64 def v16i16 : ValueType<256, 40>; // 16 x i16 vector value
65 def v32i16 : ValueType<512, 41>; // 32 x i16 vector value
66 def v64i16 : ValueType<1024, 42>; // 64 x i16 vector value
67 def v128i16 : ValueType<2048, 43>; // 128 x i16 vector value
[all …]
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Lanai/
H A DLanaiCallingConv.td19 // Promote i8/i16 args to i32
20 CCIfType<[i8, i16], CCPromoteToType<i32>>,
32 // Promote i8/i16 args to i32
33 CCIfType<[ i8, i16 ], CCPromoteToType<i32>>,
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/X86/
H A DX86CallingConv.td81 // Promote i1/i8/i16/v1i1 arguments to i32.
82 CCIfType<[i1, i8, i16, v1i1], CCPromoteToType<i32>>,
158 // Promote v16i1 arguments to i16.
159 CCIfType<[v16i1], CCPromoteToType<i16>>,
166 CCIfType<[i16], CCAssignToReg<RC.GPR_16>>,
209 // the way LLVM does multiple return values -- a return of {i16,i8} would end
212 // values into an i16 (which uses AX, and thus AL:AH).
219 CCIfType<[i16], CCAssignToReg<[AX, DX, CX]>>,
284 CCIfType<[i16], CCAssignToReg<[AX, DX, CX]>>,
313 CCIfType<[i8, i16], CCPromoteToType<i32>>,
[all …]
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/VE/
H A DVECallingConv.td31 // Promote i1/i8/i16/i32 arguments to i64.
32 CCIfType<[i1, i8, i16, i32], CCPromoteToType<i64>>,
62 // Promote i1/i8/i16/i32 arguments to i64.
63 CCIfType<[i1, i8, i16, i32], CCPromoteToType<i64>>,
79 // Promote i1/i8/i16/i32 return values to i64.
80 CCIfType<[i1, i8, i16, i32], CCPromoteToType<i64>>,
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Mips/
H A DMipsCallingConv.td81 // Promote i8/i16 arguments to i32.
82 CCIfType<[i1, i8, i16], CCPromoteToType<i32>>,
96 // Promote i1/i8/i16 return values to i32.
97 CCIfType<[i1, i8, i16], CCPromoteToType<i32>>,
134 CCIfType<[i8, i16, i32, i64],
139 CCIfType<[i8, i16, i32], CCIfOrigArgWasNotFloat<CCPromoteToType<i64>>>,
171 CCIfType<[i8, i16, i32, i64],
176 CCIfType<[i8, i16, i32], CCPromoteToType<i64>>,
205 CCIfType<[i8, i16, i32, i64], CCIfInReg<CCPromoteToType<i64>>>>,
207 CCIfType<[i8, i16, i32, i64],
[all …]
/netbsd-src/tests/include/
H A Dt_inttypes.c41 int16_t i16 = 0; in ATF_TC_BODY() local
75 PRINT(PRId16, i16); in ATF_TC_BODY()
90 PRINT(PRIi16, i16); in ATF_TC_BODY()
166 SCAN(SCNd16, i16); in ATF_TC_BODY()
181 SCAN(SCNi16, i16); in ATF_TC_BODY()

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