| /netbsd-src/sys/external/bsd/drm2/dist/drm/i915/selftests/ |
| H A D | igt_spinner.c | 26 spin->hws = i915_gem_object_create_internal(gt->i915, PAGE_SIZE); in igt_spinner_init()
27 if (IS_ERR(spin->hws)) { in igt_spinner_init()
28 err = PTR_ERR(spin->hws); in igt_spinner_init()
38 i915_gem_object_set_cache_coherency(spin->hws, I915_CACHE_LLC); in igt_spinner_init()
39 vaddr = i915_gem_object_pin_map(spin->hws, I915_MAP_WB); in igt_spinner_init()
57 i915_gem_object_unpin_map(spin->hws); in igt_spinner_init()
61 i915_gem_object_put(spin->hws); in igt_spinner_init()
71 static u64 hws_address(const struct i915_vma *hws, in hws_address() argument
74 return hws->node.start + seqno_offset(rq->fence.context); in hws_address()
100 struct i915_vma *hws, *vma; in igt_spinner_create_request() local
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| H A D | igt_spinner.h | 23 struct drm_i915_gem_object *hws; member
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| /netbsd-src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce/ |
| H A D | amdgpu_dce_hwseq.c | 37 hws->ctx
39 hws->regs->reg
43 hws->shifts->field_name, hws->masks->field_name
45 void dce_enable_fe_clock(struct dce_hwseq *hws, in dce_enable_fe_clock() argument
58 struct dce_hwseq *hws = dc->hwseq; in dce_pipe_control_lock() local
80 if (hws->masks->BLND_BLND_V_UPDATE_LOCK != 0) in dce_pipe_control_lock()
85 if (hws->wa.blnd_crtc_trigger) { in dce_pipe_control_lock()
93 void dce_set_blender_mode(struct dce_hwseq *hws, in dce_set_blender_mode() argument
125 if (hws->masks->BLND_ALPHA_MODE != 0) { in dce_set_blender_mode()
134 static void dce_disable_sram_shut_down(struct dce_hwseq *hws) in dce_disable_sram_shut_down() argument
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| /netbsd-src/external/gpl3/gdb/dist/sim/testsuite/bfin/ |
| H A D | hwloop-branch-in.s | 51 loadsym R1, hws;
56 test_rts hws, 0, 1, 1, 1, 0
57 test_rts hws, 1, 1, 1, 1, 0
58 test_rts hws, 2, 2, 2, 2, 0
59 test_rts hws, 20, 20, 20, 20, 0
75 test_jump hws, 0, 1, 1, 1, 0
76 test_jump hws, 1, 1, 1, 1, 0
77 test_jump hws, 2, 2, 2, 2, 0
78 test_jump hws, 20, 20, 20, 20, 0
96 hws: R5 += 1; label
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| /netbsd-src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn10/ |
| H A D | amdgpu_dcn10_hw_sequencer.c | 63 hws->ctx
65 hws->regs->reg
69 hws->shifts->field_name, hws->masks->field_name
121 struct dce_hwseq *hws = dc->hwseq; in log_mpc_crc() local
484 struct dce_hwseq *hws, in dcn10_enable_power_gating_plane() argument
506 struct dce_hwseq *hws) in dcn10_disable_vga() argument
539 struct dce_hwseq *hws, in dcn10_dpp_pg_control() argument
546 if (hws->ctx->dc->debug.disable_dpp_power_gate) in dcn10_dpp_pg_control()
591 struct dce_hwseq *hws, in dcn10_hubp_pg_control() argument
598 if (hws->ctx->dc->debug.disable_hubp_power_gate) in dcn10_hubp_pg_control()
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| H A D | dcn10_hw_sequencer.h | 81 struct dce_hwseq *hws,
85 struct dce_hwseq *hws,
89 struct dce_hwseq *hws,
93 struct dce_hwseq *hws);
105 void dcn10_update_dchub(struct dce_hwseq *hws, struct dchub_init_data *dh_data);
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| H A D | amdgpu_dcn10_resource.c | 884 struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL); in dcn10_hwseq_create() local
886 if (hws) { in dcn10_hwseq_create()
887 hws->ctx = ctx; in dcn10_hwseq_create()
888 hws->regs = &hwseq_reg; in dcn10_hwseq_create()
889 hws->shifts = &hwseq_shift; in dcn10_hwseq_create()
890 hws->masks = &hwseq_mask; in dcn10_hwseq_create()
891 hws->wa.DEGVIDCN10_253 = true; in dcn10_hwseq_create()
892 hws->wa.false_optc_underflow = true; in dcn10_hwseq_create()
893 hws->wa.DEGVIDCN10_254 = true; in dcn10_hwseq_create()
895 return hws; in dcn10_hwseq_create()
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| /netbsd-src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn21/ |
| H A D | amdgpu_dcn21_hwseq.c | 45 hws->ctx
47 hws->regs->reg
51 hws->shifts->field_name, hws->masks->field_name
55 struct dce_hwseq *hws) in mmhub_update_page_table_config() argument
69 int dcn21_init_sys_ctx(struct dce_hwseq *hws, struct dc *dc, struct dc_phy_addr_space_config *pa_co… in dcn21_init_sys_ctx() argument
83 mmhub_update_page_table_config(&config, hws); in dcn21_init_sys_ctx()
92 struct dce_hwseq *hws = dc->hwseq; in dcn21_s0i3_golden_init_wa() local
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| H A D | dcn21_hwseq.h | 35 int dcn21_init_sys_ctx(struct dce_hwseq *hws,
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| H A D | amdgpu_dcn21_resource.c | 1476 struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL); in dcn21_hwseq_create() local
1478 if (hws) { in dcn21_hwseq_create()
1479 hws->ctx = ctx; in dcn21_hwseq_create()
1480 hws->regs = &hwseq_reg; in dcn21_hwseq_create()
1481 hws->shifts = &hwseq_shift; in dcn21_hwseq_create()
1482 hws->masks = &hwseq_mask; in dcn21_hwseq_create()
1483 hws->wa.DEGVIDCN21 = true; in dcn21_hwseq_create()
1485 return hws; in dcn21_hwseq_create()
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| /netbsd-src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn20/ |
| H A D | dcn20_hwseq.h | 90 struct dce_hwseq *hws);
93 struct dce_hwseq *hws,
96 struct dce_hwseq *hws,
100 struct dce_hwseq *hws,
119 struct dce_hwseq *hws,
127 struct dce_hwseq *hws,
133 void dcn20_dccg_init(struct dce_hwseq *hws);
134 int dcn20_init_sys_ctx(struct dce_hwseq *hws,
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| H A D | amdgpu_dcn20_hwseq.c | 61 hws->ctx
63 hws->regs->reg
67 hws->shifts->field_name, hws->masks->field_name
188 struct dce_hwseq *hws, in dcn20_enable_power_gating_plane() argument
228 void dcn20_dccg_init(struct dce_hwseq *hws) in dcn20_dccg_init() argument
253 struct dce_hwseq *hws) in dcn20_disable_vga() argument
280 struct dce_hwseq *hws = dc->hwseq; in dcn20_init_blank() local
328 hws->funcs.wait_for_blank_complete(opp); in dcn20_init_blank()
332 struct dce_hwseq *hws, in dcn20_dsc_pg_control() argument
340 if (hws->ctx->dc->debug.disable_dsc_power_gate) in dcn20_dsc_pg_control()
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| /netbsd-src/sys/external/bsd/drm2/dist/drm/amd/display/dc/inc/ |
| H A D | hw_sequencer_private.h | 106 void (*disable_vga)(struct dce_hwseq *hws);
112 void (*enable_power_gating_plane)(struct dce_hwseq *hws,
114 void (*dpp_pg_control)(struct dce_hwseq *hws,
117 void (*hubp_pg_control)(struct dce_hwseq *hws,
120 void (*dsc_pg_control)(struct dce_hwseq *hws,
140 void (*dccg_init)(struct dce_hwseq *hws);
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| H A D | hw_sequencer.h | 73 void (*update_dchub)(struct dce_hwseq *hws,
144 int (*init_sys_ctx)(struct dce_hwseq *hws,
147 void (*init_vm_ctx)(struct dce_hwseq *hws,
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| /netbsd-src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce120/ |
| H A D | amdgpu_dce120_hw_sequencer.c | 46 hws->ctx
48 hws->regs->reg
52 hws->shifts->field_name, hws->masks->field_name
202 struct dce_hwseq *hws, in dce120_update_dchub() argument
258 bool dce121_xgmi_enabled(struct dce_hwseq *hws) in dce121_xgmi_enabled() argument
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| H A D | amdgpu_dce120_resource.c | 786 struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL); in dce120_hwseq_create() local
788 if (hws) { in dce120_hwseq_create()
789 hws->ctx = ctx; in dce120_hwseq_create()
790 hws->regs = &hwseq_reg; in dce120_hwseq_create()
791 hws->shifts = &hwseq_shift; in dce120_hwseq_create()
792 hws->masks = &hwseq_mask; in dce120_hwseq_create()
794 return hws; in dce120_hwseq_create()
800 struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL); in dce121_hwseq_create() local
802 if (hws) { in dce121_hwseq_create()
803 hws->ctx = ctx; in dce121_hwseq_create()
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| H A D | dce120_hw_sequencer.h | 36 bool dce121_xgmi_enabled(struct dce_hwseq *hws);
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| /netbsd-src/sys/external/bsd/drm2/dist/drm/i915/gt/ |
| H A D | selftest_hangcheck.c | 53 struct drm_i915_gem_object *hws; member
74 h->hws = i915_gem_object_create_internal(gt->i915, PAGE_SIZE); in hang_init()
75 if (IS_ERR(h->hws)) { in hang_init()
76 err = PTR_ERR(h->hws); in hang_init()
86 i915_gem_object_set_cache_coherency(h->hws, I915_CACHE_LLC); in hang_init()
87 vaddr = i915_gem_object_pin_map(h->hws, I915_MAP_WB); in hang_init()
105 i915_gem_object_unpin_map(h->hws); in hang_init()
109 i915_gem_object_put(h->hws); in hang_init()
115 static u64 hws_address(const struct i915_vma *hws, in hws_address() argument
118 return hws->node.start + offset_in_page(sizeof(u32)*rq->fence.context); in hws_address()
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| /netbsd-src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce110/ |
| H A D | amdgpu_dce110_hw_sequencer.c | 81 hws->ctx
86 hws->regs->reg
90 hws->shifts->field_name, hws->masks->field_name
704 static bool is_panel_backlight_on(struct dce_hwseq *hws) in is_panel_backlight_on() argument
713 static bool is_panel_powered_on(struct dce_hwseq *hws) in is_panel_powered_on() argument
895 struct dce_hwseq *hws = ctx->dc->hwseq; in dce110_edp_backlight_control() local
904 if (enable && is_panel_backlight_on(hws)) { in dce110_edp_backlight_control()
1056 struct dce_hwseq *hws = link->dc->hwseq; in dce110_unblank_stream() local
1066 hws->funcs.edp_backlight_control(link, true); in dce110_unblank_stream()
1074 struct dce_hwseq *hws = link->dc->hwseq; in dce110_blank_stream() local
[all …]
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| H A D | amdgpu_dce110_resource.c | 558 struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL); in dce110_hwseq_create() local
560 if (hws) { in dce110_hwseq_create()
561 hws->ctx = ctx; in dce110_hwseq_create()
562 hws->regs = ASIC_REV_IS_STONEY(ctx->asic_id.hw_internal_rev) ? in dce110_hwseq_create()
564 hws->shifts = &hwseq_shift; in dce110_hwseq_create()
565 hws->masks = &hwseq_mask; in dce110_hwseq_create()
566 hws->wa.blnd_crtc_trigger = true; in dce110_hwseq_create()
568 return hws; in dce110_hwseq_create()
1105 struct dce_hwseq *hws = dc->hwseq; in dce110_acquire_underlay() local
1126 hws->funcs.enable_display_power_gating( in dce110_acquire_underlay()
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| /netbsd-src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce100/ |
| H A D | amdgpu_dce100_resource.c | 504 struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL); in dce100_hwseq_create() local
506 if (hws) { in dce100_hwseq_create()
507 hws->ctx = ctx; in dce100_hwseq_create()
508 hws->regs = &hwseq_reg; in dce100_hwseq_create()
509 hws->shifts = &hwseq_shift; in dce100_hwseq_create()
510 hws->masks = &hwseq_mask; in dce100_hwseq_create()
512 return hws; in dce100_hwseq_create()
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| /netbsd-src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce80/ |
| H A D | amdgpu_dce80_resource.c | 627 struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL); in dce80_hwseq_create() local
629 if (hws) { in dce80_hwseq_create()
630 hws->ctx = ctx; in dce80_hwseq_create()
631 hws->regs = &hwseq_reg; in dce80_hwseq_create()
632 hws->shifts = &hwseq_shift; in dce80_hwseq_create()
633 hws->masks = &hwseq_mask; in dce80_hwseq_create()
635 return hws; in dce80_hwseq_create()
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| /netbsd-src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce112/ |
| H A D | amdgpu_dce112_resource.c | 531 struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL); in dce112_hwseq_create() local
533 if (hws) { in dce112_hwseq_create()
534 hws->ctx = ctx; in dce112_hwseq_create()
535 hws->regs = &hwseq_reg; in dce112_hwseq_create()
536 hws->shifts = &hwseq_shift; in dce112_hwseq_create()
537 hws->masks = &hwseq_mask; in dce112_hwseq_create()
539 return hws; in dce112_hwseq_create()
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| /netbsd-src/sys/external/bsd/drm/dist/shared-core/ |
| H A D | i915_dma.c | 801 drm_i915_hws_addr_t *hws = data; in i915_set_status_page() local
811 DRM_DEBUG("set status page addr 0x%08x\n", (u32)hws->addr); in i915_set_status_page()
813 dev_priv->status_gfx_addr = hws->addr & (0x1ffff<<12); in i915_set_status_page()
815 dev_priv->hws_map.offset = dev->agp->base + hws->addr; in i915_set_status_page()
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| /netbsd-src/sys/external/bsd/drm2/dist/drm/i915/ |
| H A D | i915_gpu_error.h | 77 u32 hws; member
|