| /netbsd-src/sys/arch/evbarm/ifpga/ |
| H A D | ifpga_intr.c | 301 int oldirqstate, pcpl, irq, ibit, hwpend; in ifpga_intr_dispatch() local
306 hwpend = ifpga_iintsrc_read(); in ifpga_intr_dispatch()
312 intr_enabled &= ~hwpend; in ifpga_intr_dispatch()
316 while ((ifpga_iintsrc_read() & hwpend) != 0) in ifpga_intr_dispatch()
319 while (hwpend != 0) { in ifpga_intr_dispatch()
320 irq = ffs(hwpend) - 1; in ifpga_intr_dispatch()
323 hwpend &= ~ibit; in ifpga_intr_dispatch()
348 hwpend |= (ifpga_ipending & IFPGA_INTR_HWMASK) & ~pcpl; in ifpga_intr_dispatch()
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| H A D | ifpga_intr.h | 70 int oldirqstate, hwpend; in ifpga_splx() local
77 hwpend = (ifpga_ipending & IFPGA_INTR_HWMASK) & ~new; in ifpga_splx()
78 if (hwpend != 0) { in ifpga_splx()
79 intr_enabled |= hwpend; in ifpga_splx()
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| /netbsd-src/sys/arch/arm/xscale/ |
| H A D | i80321_intr.h | 70 int oldirqstate, hwpend; in i80321_splx() local
77 hwpend = (i80321_ipending & ICU_INT_HWMASK) & ~i80321_imask[new]; in i80321_splx()
78 if (hwpend != 0) { in i80321_splx()
80 intr_enabled |= hwpend; in i80321_splx()
83 if (__predict_false(hwpend & INT_HPIMASK)) in i80321_splx()
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| H A D | i80321_icu.c | 355 int oldirqstate, irq, ibit, hwpend; in i80321_intr_dispatch() local
363 hwpend = i80321_iintsrc_read(); in i80321_intr_dispatch()
369 intr_enabled &= ~hwpend; in i80321_intr_dispatch()
376 while (hwpend != 0) { in i80321_intr_dispatch()
379 if (__predict_false(hwpend & INT_HPIMASK)) in i80321_intr_dispatch()
383 irq = ffs(hwpend) - 1; in i80321_intr_dispatch()
386 hwpend &= ~ibit; in i80321_intr_dispatch()
451 hwpend |= ((i80321_ipending & ICU_INT_HWMASK) & ~imask); in i80321_intr_dispatch()
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| H A D | ixp425_intr.h | 67 int oldirqstate, hwpend; in ixp425_splx() local
74 hwpend = (ixp425_ipending & IXP425_INT_HWMASK) & ~ixp425_imask[ipl]; in ixp425_splx()
75 if (hwpend != 0) { in ixp425_splx()
77 intr_enabled |= hwpend; in ixp425_splx()
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| H A D | becc_intr.h | 77 uint32_t oldirqstate, hwpend; in becc_splx() local
87 hwpend = becc_ipending & ~new; in becc_splx()
88 if (hwpend != 0) { in becc_splx()
90 intr_enabled |= hwpend; in becc_splx()
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| H A D | ixp425_intr.c | 389 int oldirqstate, irq, ibit, hwpend; in ixp425_intr_dispatch() local
394 hwpend = ixp425_irq_read(); in ixp425_intr_dispatch()
400 intr_enabled &= ~hwpend; in ixp425_intr_dispatch()
403 while (hwpend != 0) { in ixp425_intr_dispatch()
404 irq = ffs(hwpend) - 1; in ixp425_intr_dispatch()
407 hwpend &= ~ibit; in ixp425_intr_dispatch()
453 hwpend |= ((ixp425_ipending & IXP425_INT_HWMASK) & ~imask); in ixp425_intr_dispatch()
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| H A D | becc_icu.c | 339 uint32_t oldirqstate, irq, ibit, hwpend; in becc_intr_dispatch() local
344 hwpend = becc_icsr_read(); in becc_intr_dispatch()
350 intr_enabled &= ~hwpend; in becc_intr_dispatch()
353 while (hwpend != 0) { in becc_intr_dispatch()
354 irq = ffs(hwpend) - 1; in becc_intr_dispatch()
357 hwpend &= ~ibit; in becc_intr_dispatch()
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| /netbsd-src/sys/arch/arm/footbridge/ |
| H A D | footbridge_irqhandler.c | 284 int oldirqstate, irq, ibit, hwpend; in footbridge_intr_dispatch() local
289 hwpend = footbridge_intstatus(); in footbridge_intr_dispatch()
295 intr_enabled &= ~hwpend; in footbridge_intr_dispatch()
298 while (hwpend != 0) { in footbridge_intr_dispatch()
300 irq = ffs(hwpend) - 1; in footbridge_intr_dispatch()
303 hwpend &= ~ibit; in footbridge_intr_dispatch()
336 hwpend |= (footbridge_ipending & ICU_INT_HWMASK) & ~imask; in footbridge_intr_dispatch()
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| H A D | footbridge_intr.h | 103 int oldirqstate, hwpend; in footbridge_splx() local
110 hwpend = footbridge_ipending & ICU_INT_HWMASK & ~footbridge_imask[ipl]; in footbridge_splx()
111 if (hwpend != 0) { in footbridge_splx()
113 intr_enabled |= hwpend; in footbridge_splx()
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| /netbsd-src/sys/arch/mips/cavium/ |
| H A D | octeon_intr.c | 487 uint64_t hwpend[2] = { 0, 0 }; in octeon_iointr() local
492 hwpend[0] = mips3_ld(cpu->cpu_ip4_sum0) in octeon_iointr()
494 hwpend[1] = sum1 & cpu->cpu_ip4_enable[1]; in octeon_iointr()
496 hwpend[0] = mips3_ld(cpu->cpu_ip3_sum0) in octeon_iointr()
498 hwpend[1] = sum1 & cpu->cpu_ip3_enable[1]; in octeon_iointr()
500 hwpend[0] = mips3_ld(cpu->cpu_ip2_sum0) in octeon_iointr()
502 hwpend[1] = sum1 & cpu->cpu_ip2_enable[1]; in octeon_iointr()
507 while (hwpend[bank] != 0) { in octeon_iointr()
508 const int bit = ffs64(hwpend[bank]) - 1; in octeon_iointr()
510 hwpend[bank] &= ~__BIT(bit); in octeon_iointr()
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| /netbsd-src/sys/arch/arm/ixp12x0/ |
| H A D | ixp12x0_intr.c | 383 uint32_t hwpend; in ixp12x0_intr_dispatch() local
389 hwpend = ixp12x0_irq_read(); in ixp12x0_intr_dispatch()
393 ixp12x0_set_intrmask(imask[ppl] | hwpend, pci_imask[ppl] | pci_hwpend); in ixp12x0_intr_dispatch()
395 hwpend &= ~imask[ppl]; in ixp12x0_intr_dispatch()
398 while (hwpend) { in ixp12x0_intr_dispatch()
399 irq = ffs(hwpend) - 1; in ixp12x0_intr_dispatch()
410 hwpend &= ~ibit; in ixp12x0_intr_dispatch()
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| /netbsd-src/sys/arch/evbarm/iq80310/ |
| H A D | iq80310_intr.c | 419 int oldirqstate, pcpl, irq, ibit, hwpend, rv; in iq80310_intr_dispatch() local
432 for (hwpend = iq80310_intstat_read(); hwpend != 0;) { in iq80310_intr_dispatch()
433 irq = ffs(hwpend) - 1; in iq80310_intr_dispatch()
440 hwpend &= ~ibit; in iq80310_intr_dispatch()
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