Searched refs:hasMVEIntegerOps (Results 1 – 13 of 13) sorted by relevance
106 if (ST->hasMVEIntegerOps()) in getPreferredAddressingMode()386 (ST->hasNEON() || ST->hasMVEIntegerOps())) { in getCFInstrCost()427 if ((ST->hasMVEIntegerOps() && in getCastInstrCost()475 if (SrcTy.isVector() && ST->hasMVEIntegerOps()) { in getCastInstrCost()504 if (SrcTy.isVector() && ST->hasMVEIntegerOps()) { in getCastInstrCost()739 if (SrcTy.isVector() && ST->hasMVEIntegerOps()) { in getCastInstrCost()762 if (ISD == ISD::TRUNCATE && ST->hasMVEIntegerOps() && in getCastInstrCost()793 int BaseCost = ST->hasMVEIntegerOps() && Src->isVectorTy() in getCastInstrCost()823 if (ST->hasMVEIntegerOps() && (Opcode == Instruction::InsertElement || in getVectorInstrCost()936 if (ST->hasMVEIntegerOps() && ValTy->isVectorTy() && in getCmpSelInstrCost()[all …]
149 if (ST->hasMVEIntegerOps()) in getNumberOfRegisters()166 if (ST->hasMVEIntegerOps()) in getRegisterBitWidth()
177 if (Subtarget.hasMVEIntegerOps() && in EmitTargetCodeForMemcpy()308 if (Subtarget.hasMVEIntegerOps() && in EmitTargetCodeForMemset()
307 if (!STI.isThumb2() || !STI.hasMVEIntegerOps()) in runOnMachineFunction()
786 if (Subtarget->hasMVEIntegerOps()) in ARMTargetLowering()820 if (Subtarget->hasMVEIntegerOps() || Subtarget->hasNEON()) { in ARMTargetLowering()978 if (Subtarget->hasNEON() || Subtarget->hasMVEIntegerOps()) { in ARMTargetLowering()995 if (Subtarget->hasMVEIntegerOps()) { in ARMTargetLowering()1139 if (Subtarget->hasMVEIntegerOps()) in ARMTargetLowering()1520 if (Subtarget->hasMVEIntegerOps()) in ARMTargetLowering()1821 if (Subtarget->hasMVEIntegerOps() && in getSetCCResultType()1836 if (Subtarget->hasNEON() || Subtarget->hasMVEIntegerOps()) { in getRegClassFor()6359 if (ST->hasMVEIntegerOps()) { in Expand64BitShift()6444 assert(ST->hasMVEIntegerOps() && in LowerVSETCC()[all …]
377 if (!ST->hasMVEIntegerOps()) in runOnFunction()
142 if (!ST->hasMVEIntegerOps() || !ST->hasV8_1MMainlineOps()) { in runOnLoop()
624 bool hasMVEIntegerOps() const { return HasMVEIntegerOps; } in hasMVEIntegerOps() function
32 def HasMVEInt : Predicate<"Subtarget->hasMVEIntegerOps()">,
471 return 1 + MF.getSubtarget<ARMSubtarget>().hasMVEIntegerOps();511 return 1 + MF.getSubtarget<ARMSubtarget>().hasMVEIntegerOps();
1163 if (!ST->hasMVEIntegerOps()) in runOnFunction()
3047 if (!Subtarget->hasMVEIntegerOps()) in tryInsertVectorElt()3782 if (Subtarget->hasMVEIntegerOps() && tryMVEIndexedLoad(N)) in Select()3796 if (Subtarget->hasMVEIntegerOps() && tryMVEIndexedLoad(N)) in Select()
1209 Subtarget.hasMVEIntegerOps()) { in storeRegToStackSlot()1448 Subtarget.hasMVEIntegerOps()) { in loadRegFromStackSlot()