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Searched refs:hasInterval (Results 1 – 18 of 18) sorted by relevance

/netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/
H A DLiveIntervals.h115 if (hasInterval(Reg)) in getInterval()
125 bool hasInterval(Register Reg) const { in hasInterval() function
132 assert(!hasInterval(Reg) && "Interval already exists!"); in createEmptyInterval()
H A DLiveStacks.h78 bool hasInterval(int Slot) const { return S2IMap.count(Slot); } in hasInterval() function
/netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/
H A DRegAllocBase.cpp150 assert(LIS->hasInterval(Reg)); in allocatePhysRegs()
H A DRenameIndependentSubregs.cpp395 if (!LIS->hasInterval(Reg)) in runOnMachineFunction()
H A DLiveRangeEdit.cpp386 if (LIS.hasInterval(Reg) && MRI.reg_nodbg_empty(Reg)) { in eliminateDeadDef()
H A DLiveDebugVariables.cpp797 if (!LIS->hasInterval(Reg)) { in handleDebugValue()
1010 if (!LIS.hasInterval(DstReg)) in addDefsFromCopies()
1086 if (LIS.hasInterval(LocMO.getReg())) { in computeIntervals()
H A DStackSlotColoring.cpp169 if (!LS->hasInterval(FI)) in ScanForSpillSlotRefs()
H A DLiveIntervals.cpp166 if (hasInterval(Reg)) in print()
1553 if (Reg.isVirtual() && hasInterval(Reg) && !MO.isUndef()) { in handleMoveIntoNewBundle()
1685 !hasInterval(MOI->getReg())) { in repairIntervalsInRange()
H A DMachineVerifier.cpp2044 if (LiveStks && LiveStks->hasInterval(MO->getIndex()) && in visitMachineOperand()
2191 if (LiveInts->hasInterval(Reg)) { in checkLiveness()
2290 if (LiveInts->hasInterval(Reg)) { in checkLiveness()
2710 if (!LiveInts->hasInterval(Reg)) { in verifyLiveIntervals()
H A DMachineBasicBlock.cpp1215 if (PHISrcRegs.count(Reg) || !LIS->hasInterval(Reg)) in SplitCriticalEdge()
H A DInlineSpiller.cpp734 assert(LIS.hasInterval(Reg) && in reMaterializeAll()
H A DModuloSchedule.cpp345 if (!LIS.hasInterval(ToReg)) in replaceRegUsesAfterLoop()
H A DRegAllocGreedy.cpp1551 if (!LIS->hasInterval(Evictor)) in splitCanCauseEvictionChain()
H A DRegisterCoalescer.cpp3781 if (!LIS->hasInterval(reg)) in lateLiveIntervalUpdate()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
H A DGCNRegPressure.cpp31 if (!LIS.hasInterval(Reg)) in printLivesAt()
269 if (!LIS.hasInterval(Reg)) in getLiveRegs()
H A DGCNRegPressure.h227 if (!LIS.hasInterval(Reg)) in getLiveRegMap()
H A DGCNNSAReassign.cpp214 if (!LIS->hasInterval(Reg)) in CheckNSA()
H A DSIRegisterInfo.cpp2391 if (!LIS->hasInterval(Reg)) in findReachingDef()