Searched refs:h_sync_width (Results 1 – 16 of 16) sorted by relevance
170 uint32_t h_sync_width; member
183 OTG_H_SYNC_A_END, patched_crtc_timing.h_sync_width); in optc1_program_timing()557 if (timing->h_sync_width < optc1->min_h_sync_width || in optc1_validate_timing()1261 hw_crtc_timing->h_sync_width = s.h_sync_a_end - s.h_sync_a_start; in optc1_get_hw_timing()
445 hw_crtc_timing.h_sync_width; in enc1_stream_encoder_dp_set_stream_attribute()448 h_active_start = hw_crtc_timing.h_sync_width + h_back_porch; in enc1_stream_encoder_dp_set_stream_attribute()463 hw_crtc_timing.h_sync_width, in enc1_stream_encoder_dp_set_stream_attribute()
487 hw_crtc_timing.h_sync_width; in dce110_stream_encoder_dp_set_stream_attribute()490 h_active_start = hw_crtc_timing.h_sync_width + h_back_porch; in dce110_stream_encoder_dp_set_stream_attribute()508 hw_crtc_timing.h_sync_width, in dce110_stream_encoder_dp_set_stream_attribute()
91 u8 h_sync_width; /* lower 8 bits (pixels) */ member
868 dtd->part2.h_sync_width = h_sync_len & 0xff; in intel_sdvo_get_dtd_from_mode()895 mode.hsync_end = mode.hsync_start + dtd->part2.h_sync_width; in intel_sdvo_get_mode_from_dtd()
720 uint32_t h_sync_width; member
322 bp_params.h_sync_width = patched_crtc_timing.h_sync_width; in dce110_timing_generator_program_timing_generator()1167 timing->h_sync_width); in dce110_timing_generator_validate_timing()
331 timing->h_sync_width, in dce110_timing_generator_v_program_blanking()
516 params.h_syncwidth = cpu_to_le16((uint16_t)bp_params->h_sync_width); in set_crtc_using_dtd_timing_v3()
1760 params.usH_SyncWidth = cpu_to_le16((uint16_t)(bp_params->h_sync_width)); in set_crtc_timing_v1()1845 params.usH_SyncWidth = cpu_to_le16((uint16_t)bp_params->h_sync_width); in set_crtc_using_dtd_timing_v3()
898 info->lcd_timing.horizontal_sync_width = le16_to_cpu(lvds->lcd_timing.h_sync_width); in get_embedded_panel_info_v2_1()
126 timing->h_sync_width < tg110->min_h_sync_width || in dce120_timing_generator_validate_timing()
1112 if (crtc_timing->h_sync_width != hw_crtc_timing.h_sync_width) in dc_validate_seamless_boot_timing()
438 uint16_t h_sync_width; member
3824 timing_out->h_sync_width = in fill_stream_properties_from_drm_display_mode()