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Searched refs:gpc (Results 1 – 25 of 57) sorted by relevance

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/netbsd-src/sys/external/bsd/drm2/dist/drm/nouveau/nvkm/engine/gr/
H A Dnouveau_nvkm_engine_gr_ctxgp100.c61 int gpc, ppc, b, n = 0; in gp100_grctx_generate_attrib() local
63 for (gpc = 0; gpc < gr->gpc_nr; gpc++) in gp100_grctx_generate_attrib()
64 size += grctx->attrib_nr_max * gr->ppc_nr[gpc] * gr->ppc_tpc_max; in gp100_grctx_generate_attrib()
77 for (gpc = 0; gpc < gr->gpc_nr; gpc++) { in gp100_grctx_generate_attrib()
78 for (ppc = 0; ppc < gr->ppc_nr[gpc]; ppc++, n++) { in gp100_grctx_generate_attrib()
79 const u32 as = alpha * gr->ppc_tpc_nr[gpc][ppc]; in gp100_grctx_generate_attrib()
82 const u32 o = PPC_UNIT(gpc, ppc, 0); in gp100_grctx_generate_attrib()
83 if (!(gr->ppc_mask[gpc] & (1 << ppc))) in gp100_grctx_generate_attrib()
91 ao += grctx->alpha_nr_max * gr->ppc_tpc_nr[gpc][ppc]; in gp100_grctx_generate_attrib()
109 const u8 gpc = gr->sm[sm].gpc; in gp100_grctx_generate_smid_config() local
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H A Dnouveau_nvkm_engine_gr_gv100.c33 gv100_gr_trap_sm(struct gf100_gr *gr, int gpc, int tpc, int sm) in gv100_gr_trap_sm() argument
37 u32 werr = nvkm_rd32(device, TPC_UNIT(gpc, tpc, 0x730 + (sm * 0x80))); in gv100_gr_trap_sm()
38 u32 gerr = nvkm_rd32(device, TPC_UNIT(gpc, tpc, 0x734 + (sm * 0x80))); in gv100_gr_trap_sm()
47 gpc, tpc, sm, gerr, glob, werr, warp ? warp->name : ""); in gv100_gr_trap_sm()
49 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x730 + sm * 0x80), 0x00000000); in gv100_gr_trap_sm()
50 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x734 + sm * 0x80), gerr); in gv100_gr_trap_sm()
54 gv100_gr_trap_mp(struct gf100_gr *gr, int gpc, int tpc) in gv100_gr_trap_mp() argument
56 gv100_gr_trap_sm(gr, gpc, tpc, 0); in gv100_gr_trap_mp()
57 gv100_gr_trap_sm(gr, gpc, tpc, 1); in gv100_gr_trap_mp()
68 gv100_gr_init_shader_exceptions(struct gf100_gr *gr, int gpc, int tpc) in gv100_gr_init_shader_exceptions() argument
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H A Dnouveau_nvkm_engine_gr_ctxgp102.c57 int gpc, ppc, b, n = 0; in gp102_grctx_generate_attrib() local
59 for (gpc = 0; gpc < gr->gpc_nr; gpc++) in gp102_grctx_generate_attrib()
60 size += grctx->gfxp_nr * gr->ppc_nr[gpc] * gr->ppc_tpc_max; in gp102_grctx_generate_attrib()
73 for (gpc = 0; gpc < gr->gpc_nr; gpc++) { in gp102_grctx_generate_attrib()
74 for (ppc = 0; ppc < gr->ppc_nr[gpc]; ppc++, n++) { in gp102_grctx_generate_attrib()
75 const u32 as = alpha * gr->ppc_tpc_nr[gpc][ppc]; in gp102_grctx_generate_attrib()
79 const u32 o = PPC_UNIT(gpc, ppc, 0); in gp102_grctx_generate_attrib()
80 const u32 p = GPC_UNIT(gpc, 0xc44 + (ppc * 4)); in gp102_grctx_generate_attrib()
81 if (!(gr->ppc_mask[gpc] & (1 << ppc))) in gp102_grctx_generate_attrib()
90 ao += grctx->alpha_nr_max * gr->ppc_tpc_nr[gpc][ppc]; in gp102_grctx_generate_attrib()
H A Dnouveau_nvkm_engine_gr_ctxgv100.c78 int gpc, ppc, b, n = 0; in gv100_grctx_generate_attrib() local
80 for (gpc = 0; gpc < gr->gpc_nr; gpc++) in gv100_grctx_generate_attrib()
81 size += grctx->gfxp_nr * gr->ppc_nr[gpc] * gr->ppc_tpc_max; in gv100_grctx_generate_attrib()
93 for (gpc = 0; gpc < gr->gpc_nr; gpc++) { in gv100_grctx_generate_attrib()
94 for (ppc = 0; ppc < gr->ppc_nr[gpc]; ppc++, n++) { in gv100_grctx_generate_attrib()
95 const u32 as = alpha * gr->ppc_tpc_nr[gpc][ppc]; in gv100_grctx_generate_attrib()
99 const u32 o = PPC_UNIT(gpc, ppc, 0); in gv100_grctx_generate_attrib()
100 if (!(gr->ppc_mask[gpc] & (1 << ppc))) in gv100_grctx_generate_attrib()
108 ao += grctx->alpha_nr_max * gr->ppc_tpc_nr[gpc][ppc]; in gv100_grctx_generate_attrib()
162 gv100_grctx_generate_sm_id(struct gf100_gr *gr, int gpc, int tpc, int sm) in gv100_grctx_generate_sm_id() argument
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H A Dnouveau_nvkm_engine_gr_ctxgm200.c60 const u8 gpc = gr->sm[sm].gpc; in gm200_grctx_generate_smid_config() local
62 dist[sm / 4] |= ((gpc << 4) | tpc) << ((sm % 4) * 8); in gm200_grctx_generate_smid_config()
63 gpcs[gpc] |= sm << (tpc * 8); in gm200_grctx_generate_smid_config()
92 int gpc, ppc, i; in gm200_grctx_generate_dist_skip_table() local
94 for (gpc = 0; gpc < gr->gpc_nr; gpc++) { in gm200_grctx_generate_dist_skip_table()
95 for (ppc = 0; ppc < gr->ppc_nr[gpc]; ppc++) { in gm200_grctx_generate_dist_skip_table()
96 u8 ppc_tpcs = gr->ppc_tpc_nr[gpc][ppc]; in gm200_grctx_generate_dist_skip_table()
97 u8 ppc_tpcm = gr->ppc_tpc_mask[gpc][ppc]; in gm200_grctx_generate_dist_skip_table()
100 ppc_tpcm ^= gr->ppc_tpc_mask[gpc][ppc]; in gm200_grctx_generate_dist_skip_table()
101 ((u8 *)data)[gpc] |= ppc_tpcm; in gm200_grctx_generate_dist_skip_table()
H A Dnouveau_nvkm_engine_gr_ctxgf100.c1077 int gpc, tpc; in gf100_grctx_generate_attrib() local
1084 for (gpc = 0; gpc < gr->gpc_nr; gpc++) { in gf100_grctx_generate_attrib()
1085 for (tpc = 0; tpc < gr->tpc_nr[gpc]; tpc++) { in gf100_grctx_generate_attrib()
1086 const u32 o = TPC_UNIT(gpc, tpc, 0x0520); in gf100_grctx_generate_attrib()
1111 data |= gr->sm[sm++].gpc << (j * 8); in gf100_grctx_generate_r4060a8()
1280 int i, gpc; in gf100_grctx_generate_alpha_beta_tables() local
1292 for (gpc = 0; atarget && gpc < gr->gpc_nr; gpc++) { in gf100_grctx_generate_alpha_beta_tables()
1293 if (abits[gpc] < gr->tpc_nr[gpc]) { in gf100_grctx_generate_alpha_beta_tables()
1294 abits[gpc]++; in gf100_grctx_generate_alpha_beta_tables()
1300 for (gpc = 0; gpc < gr->gpc_nr; gpc++) { in gf100_grctx_generate_alpha_beta_tables()
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H A Dnouveau_nvkm_engine_gr_gf100.c1181 gf100_gr_trap_gpc_rop(struct gf100_gr *gr, int gpc) in gf100_gr_trap_gpc_rop() argument
1188 trap[0] = nvkm_rd32(device, GPC_UNIT(gpc, 0x0420)) & 0x3fffffff; in gf100_gr_trap_gpc_rop()
1189 trap[1] = nvkm_rd32(device, GPC_UNIT(gpc, 0x0434)); in gf100_gr_trap_gpc_rop()
1190 trap[2] = nvkm_rd32(device, GPC_UNIT(gpc, 0x0438)); in gf100_gr_trap_gpc_rop()
1191 trap[3] = nvkm_rd32(device, GPC_UNIT(gpc, 0x043c)); in gf100_gr_trap_gpc_rop()
1197 gpc, trap[0], error, trap[1] & 0xffff, trap[1] >> 16, in gf100_gr_trap_gpc_rop()
1199 nvkm_wr32(device, GPC_UNIT(gpc, 0x0420), 0xc0000000); in gf100_gr_trap_gpc_rop()
1242 gf100_gr_trap_mp(struct gf100_gr *gr, int gpc, int tpc) in gf100_gr_trap_mp() argument
1246 u32 werr = nvkm_rd32(device, TPC_UNIT(gpc, tpc, 0x648)); in gf100_gr_trap_mp()
1247 u32 gerr = nvkm_rd32(device, TPC_UNIT(gpc, tpc, 0x650)); in gf100_gr_trap_mp()
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H A Dnouveau_nvkm_engine_gr_ctxgm107.c926 int gpc, ppc, n = 0; in gm107_grctx_generate_attrib() local
934 for (gpc = 0; gpc < gr->gpc_nr; gpc++) { in gm107_grctx_generate_attrib()
935 for (ppc = 0; ppc < gr->ppc_nr[gpc]; ppc++, n++) { in gm107_grctx_generate_attrib()
936 const u32 as = alpha * gr->ppc_tpc_nr[gpc][ppc]; in gm107_grctx_generate_attrib()
937 const u32 bs = attrib * gr->ppc_tpc_nr[gpc][ppc]; in gm107_grctx_generate_attrib()
939 const u32 o = PPC_UNIT(gpc, ppc, 0); in gm107_grctx_generate_attrib()
940 if (!(gr->ppc_mask[gpc] & (1 << ppc))) in gm107_grctx_generate_attrib()
944 bo += grctx->attrib_nr_max * gr->ppc_tpc_nr[gpc][ppc]; in gm107_grctx_generate_attrib()
947 ao += grctx->alpha_nr_max * gr->ppc_tpc_nr[gpc][ppc]; in gm107_grctx_generate_attrib()
960 gm107_grctx_generate_sm_id(struct gf100_gr *gr, int gpc, int tpc, int sm) in gm107_grctx_generate_sm_id() argument
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H A Dnouveau_nvkm_engine_gr_ctxgf117.c262 int gpc, ppc; in gf117_grctx_generate_attrib() local
269 for (gpc = 0; gpc < gr->gpc_nr; gpc++) { in gf117_grctx_generate_attrib()
270 for (ppc = 0; ppc < gr->ppc_nr[gpc]; ppc++) { in gf117_grctx_generate_attrib()
271 const u32 a = alpha * gr->ppc_tpc_nr[gpc][ppc]; in gf117_grctx_generate_attrib()
272 const u32 b = beta * gr->ppc_tpc_nr[gpc][ppc]; in gf117_grctx_generate_attrib()
274 const u32 o = PPC_UNIT(gpc, ppc, 0); in gf117_grctx_generate_attrib()
275 if (!(gr->ppc_mask[gpc] & (1 << ppc))) in gf117_grctx_generate_attrib()
279 bo += grctx->attrib_nr_max * gr->ppc_tpc_nr[gpc][ppc]; in gf117_grctx_generate_attrib()
281 ao += grctx->alpha_nr_max * gr->ppc_tpc_nr[gpc][ppc]; in gf117_grctx_generate_attrib()
H A Dnouveau_nvkm_engine_gr_tu102.c50 nvkm_wr32(device, GPC_UNIT(gr->sm[sm].gpc, 0x0c10 + in tu102_gr_init_fs()
64 u8 bank[GPC_MAX] = {}, gpc, i, j; in tu102_gr_init_zcull() local
75 for (gpc = 0; gpc < gr->gpc_nr; gpc++) { in tu102_gr_init_zcull()
76 nvkm_wr32(device, GPC_UNIT(gpc, 0x0914), in tu102_gr_init_zcull()
77 gr->screen_tile_row_offset << 8 | gr->tpc_nr[gpc]); in tu102_gr_init_zcull()
78 nvkm_wr32(device, GPC_UNIT(gpc, 0x0910), 0x00040000 | in tu102_gr_init_zcull()
80 nvkm_wr32(device, GPC_UNIT(gpc, 0x0918), magicgpc918); in tu102_gr_init_zcull()
H A Dnouveau_nvkm_engine_gr_gf117.c136 u8 bank[GPC_MAX] = {}, gpc, i, j; in gf117_gr_init_zcull() local
147 for (gpc = 0; gpc < gr->gpc_nr; gpc++) { in gf117_gr_init_zcull()
148 nvkm_wr32(device, GPC_UNIT(gpc, 0x0914), in gf117_gr_init_zcull()
149 gr->screen_tile_row_offset << 8 | gr->tpc_nr[gpc]); in gf117_gr_init_zcull()
150 nvkm_wr32(device, GPC_UNIT(gpc, 0x0910), 0x00040000 | in gf117_gr_init_zcull()
152 nvkm_wr32(device, GPC_UNIT(gpc, 0x0918), magicgpc918); in gf117_gr_init_zcull()
H A Dnouveau_nvkm_engine_gr_ctxgk104.c938 int i, j, gpc, ppc; in gk104_grctx_generate_alpha_beta_tables() local
946 for (gpc = 0; gpc < gr->gpc_nr; gpc++) { in gk104_grctx_generate_alpha_beta_tables()
948 u32 ppc_tpcs = gr->ppc_tpc_nr[gpc][ppc]; in gk104_grctx_generate_alpha_beta_tables()
959 pmask = gr->ppc_tpc_mask[gpc][ppc]; in gk104_grctx_generate_alpha_beta_tables()
962 amask |= (u64)pmask << (gpc * 8); in gk104_grctx_generate_alpha_beta_tables()
964 pmask ^= gr->ppc_tpc_mask[gpc][ppc]; in gk104_grctx_generate_alpha_beta_tables()
965 bmask |= (u64)pmask << (gpc * 8); in gk104_grctx_generate_alpha_beta_tables()
H A Dnouveau_nvkm_engine_gr_gk104.c423 int gpc, ppc; in gk104_gr_init_ppc_exceptions() local
425 for (gpc = 0; gpc < gr->gpc_nr; gpc++) { in gk104_gr_init_ppc_exceptions()
426 for (ppc = 0; ppc < gr->ppc_nr[gpc]; ppc++) { in gk104_gr_init_ppc_exceptions()
427 if (!(gr->ppc_mask[gpc] & (1 << ppc))) in gk104_gr_init_ppc_exceptions()
429 nvkm_wr32(device, PPC_UNIT(gpc, ppc, 0x038), 0xc0000000); in gk104_gr_init_ppc_exceptions()
H A Dnouveau_nvkm_engine_gr_gp102.c94 u32 mask = 0, data, gpc; in gp102_gr_init_swdx_pes_mask() local
96 for (gpc = 0; gpc < gr->gpc_nr; gpc++) { in gp102_gr_init_swdx_pes_mask()
97 data = nvkm_rd32(device, GPC_UNIT(gpc, 0x0c50)) & 0x0000000f; in gp102_gr_init_swdx_pes_mask()
98 mask |= data << (gpc * 4); in gp102_gr_init_swdx_pes_mask()
H A Dnouveau_nvkm_engine_gr_ctxgf108.c754 int gpc, tpc; in gf108_grctx_generate_attrib() local
761 for (gpc = 0; gpc < gr->gpc_nr; gpc++) { in gf108_grctx_generate_attrib()
762 for (tpc = 0; tpc < gr->tpc_nr[gpc]; tpc++) { in gf108_grctx_generate_attrib()
766 const u32 o = TPC_UNIT(gpc, tpc, 0x500); in gf108_grctx_generate_attrib()
H A Dnouveau_nvkm_engine_gr_gm107.c299 gm107_gr_init_shader_exceptions(struct gf100_gr *gr, int gpc, int tpc) in gm107_gr_init_shader_exceptions() argument
302 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x644), 0x00dffffe); in gm107_gr_init_shader_exceptions()
303 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x64c), 0x00000005); in gm107_gr_init_shader_exceptions()
307 gm107_gr_init_504430(struct gf100_gr *gr, int gpc, int tpc) in gm107_gr_init_504430() argument
310 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x430), 0xc0000000); in gm107_gr_init_504430()
H A Dnouveau_nvkm_engine_gr_ctxtu102.c39 tu102_grctx_generate_sm_id(struct gf100_gr *gr, int gpc, int tpc, int sm) in tu102_grctx_generate_sm_id() argument
42 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x608), sm); in tu102_grctx_generate_sm_id()
43 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x088), sm); in tu102_grctx_generate_sm_id()
H A Dnouveau_nvkm_engine_gr_gp100.c77 gp100_gr_init_shader_exceptions(struct gf100_gr *gr, int gpc, int tpc) in gp100_gr_init_shader_exceptions() argument
80 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x644), 0x00dffffe); in gp100_gr_init_shader_exceptions()
81 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x64c), 0x00000105); in gp100_gr_init_shader_exceptions()
H A Dgf100.h130 u8 gpc; member
176 void (*init_tex_hww_esr)(struct gf100_gr *, int gpc, int tpc);
177 void (*init_504430)(struct gf100_gr *, int gpc, int tpc);
178 void (*init_shader_exceptions)(struct gf100_gr *, int gpc, int tpc);
181 void (*trap_mp)(struct gf100_gr *, int gpc, int tpc);
/netbsd-src/sys/external/gpl2/dts/dist/arch/mips/boot/dts/ingenic/
H A Dqi_lb60.dts114 col-gpios = <&gpc 10 0>, <&gpc 11 0>, <&gpc 12 0>, <&gpc 13 0>,
115 <&gpc 14 0>, <&gpc 15 0>, <&gpc 16 0>, <&gpc 17 0>;
186 sck-gpios = <&gpc 23 GPIO_ACTIVE_HIGH>;
187 mosi-gpios = <&gpc 22 GPIO_ACTIVE_HIGH>;
188 cs-gpios = <&gpc 21 GPIO_ACTIVE_LOW>;
196 status-gpios = <&gpc 27 GPIO_ACTIVE_LOW>;
268 rb-gpios = <&gpc 30 GPIO_ACTIVE_HIGH>;
H A Dcu1830-neo.dts29 gpios = <&gpc 17 GPIO_ACTIVE_HIGH>;
40 mosi-gpios = <&gpc 12 GPIO_ACTIVE_HIGH>;
41 miso-gpios = <&gpc 11 GPIO_ACTIVE_HIGH>;
42 sck-gpios = <&gpc 15 GPIO_ACTIVE_HIGH>;
43 cs-gpios = <&gpc 16 GPIO_ACTIVE_HIGH>;
73 reset-gpios = <&gpc 13 GPIO_ACTIVE_LOW>;
153 interrupt-parent = <&gpc>;
H A Drs90.dts61 gpios = <&gpc 10 GPIO_ACTIVE_LOW>;
67 gpios = <&gpc 11 GPIO_ACTIVE_LOW>;
85 gpios = <&gpc 31 GPIO_ACTIVE_LOW>;
91 gpios = <&gpc 30 GPIO_ACTIVE_LOW>;
97 gpios = <&gpc 12 GPIO_ACTIVE_LOW>;
130 enable-gpios = <&gpc 15 GPIO_ACTIVE_HIGH>;
238 cd-gpios = <&gpc 20 GPIO_ACTIVE_LOW>;
268 rb-gpios = <&gpc 27 GPIO_ACTIVE_HIGH>;
H A Dcu1000-neo.dts56 interrupt-parent = <&gpc>;
73 reset-gpios = <&gpc 17 GPIO_ACTIVE_LOW>;
149 interrupt-parent = <&gpc>;
166 snps,reset-gpio = <&gpc 23 GPIO_ACTIVE_LOW>; /* PC23 */
/netbsd-src/sys/external/gpl2/dts/dist/arch/arm/boot/dts/
H A Ds3c64xx-pinctrl.dtsi33 gpc: gpc { label
214 samsung,pins = "gpc-0", "gpc-1", "gpc-2";
220 samsung,pins = "gpc-3";
226 samsung,pins = "gpc-4", "gpc-5", "gpc-6";
232 samsung,pins = "gpc-7";
305 samsung,pins = "gpc-4";
311 samsung,pins = "gpc-5";
354 samsung,pins = "gpc-4", "gpc-5", "gpc-6", "gph-6",
H A Dimx6qp.dtsi84 &gpc {
85 compatible = "fsl,imx6qp-gpc", "fsl,imx6q-gpc";

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