Home
last modified time | relevance | path

Searched refs:getVectorMinNumElements (Results 1 – 15 of 15) sorted by relevance

/netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/
H A DValueTypes.h324 unsigned getVectorMinNumElements() const { in getVectorMinNumElements() function
425 unsigned NElts = getVectorMinNumElements(); in isPow2VectorType()
/netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/Support/
H A DMachineValueType.h481 unsigned NElts = getVectorMinNumElements(); in isPow2VectorType()
656 unsigned getVectorMinNumElements() const { in getVectorMinNumElements() function
810 return ElementCount::get(getVectorMinNumElements(), isScalableVector()); in getVectorElementCount()
815 return getVectorMinNumElements(); in getVectorNumElements()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeVectorTypes.cpp1266 DAG.getVectorIdxConstant(IdxVal + LoVT.getVectorMinNumElements(), dl)); in SplitVecRes_EXTRACT_SUBVECTOR()
1280 unsigned VecElems = VecVT.getVectorMinNumElements(); in SplitVecRes_INSERT_SUBVECTOR()
1281 unsigned SubElems = SubVecVT.getVectorMinNumElements(); in SplitVecRes_INSERT_SUBVECTOR()
1282 unsigned LoElems = LoVT.getVectorMinNumElements(); in SplitVecRes_INSERT_SUBVECTOR()
1574 unsigned LoNumElts = Lo.getValueType().getVectorMinNumElements(); in SplitVecRes_INSERT_VECTOR_ELT()
1660 DAG.getVScale(dl, EltVT, StepVal * LoVT.getVectorMinNumElements()); in SplitVecRes_STEP_VECTOR()
2393 uint64_t LoElts = Lo.getValueType().getVectorMinNumElements(); in SplitVecOp_INSERT_SUBVECTOR()
2419 uint64_t LoElts = Lo.getValueType().getVectorMinNumElements(); in SplitVecOp_EXTRACT_SUBVECTOR()
2423 assert(IdxVal + SubVT.getVectorMinNumElements() <= LoElts && in SplitVecOp_EXTRACT_SUBVECTOR()
2443 uint64_t LoElts = Lo.getValueType().getVectorMinNumElements(); in SplitVecOp_EXTRACT_VECTOR_ELT()
[all …]
H A DSelectionDAG.cpp4510 unsigned IdentityIndex = i * Op.getValueType().getVectorMinNumElements(); in foldCONCAT_VECTORS()
4937 assert(VT.getVectorMinNumElements() < in getNode()
4938 Operand.getValueType().getVectorMinNumElements() && in getNode()
5845 VT.getVectorMinNumElements() <= N1VT.getVectorMinNumElements()) && in getNode()
5849 (VT.getVectorMinNumElements() + N2C->getZExtValue()) <= in getNode()
5850 N1VT.getVectorMinNumElements()) && in getNode()
5868 unsigned Factor = VT.getVectorMinNumElements(); in getNode()
6068 VT.getVectorMinNumElements() >= N2VT.getVectorMinNumElements()) && in getNode()
6073 (N2VT.getVectorMinNumElements() + in getNode()
6075 VT.getVectorMinNumElements()) && in getNode()
[all …]
H A DDAGCombiner.cpp11851 unsigned DstElts = N0.getValueType().getVectorMinNumElements(); in visitSIGN_EXTEND_INREG()
11852 unsigned SrcElts = N00.getValueType().getVectorMinNumElements(); in visitSIGN_EXTEND_INREG()
19896 N->getOperand(0).getValueType().getVectorMinNumElements(); in visitCONCAT_VECTORS()
19944 (IndexC->getZExtValue() % SubVT.getVectorMinNumElements()) == 0) { in getSubVectorSrc()
19945 uint64_t SubIdx = IndexC->getZExtValue() / SubVT.getVectorMinNumElements(); in getSubVectorSrc()
20138 unsigned NumElts = VT.getVectorMinNumElements(); in narrowExtractedVectorLoad()
20206 unsigned SrcNumElts = SrcVT.getVectorMinNumElements(); in visitEXTRACT_SUBVECTOR()
20207 unsigned DestNumElts = V.getValueType().getVectorMinNumElements(); in visitEXTRACT_SUBVECTOR()
20253 unsigned ExtNumElts = NVT.getVectorMinNumElements(); in visitEXTRACT_SUBVECTOR()
20260 unsigned ConcatSrcNumElts = ConcatSrcVT.getVectorMinNumElements(); in visitEXTRACT_SUBVECTOR()
[all …]
H A DTargetLowering.cpp7783 unsigned NElts = VecVT.getVectorMinNumElements(); in clampDynamicVectorIndex()
8767 if (TrailingElts > VT.getVectorMinNumElements()) { in expandVectorSplice()
H A DSelectionDAGBuilder.cpp748 unsigned IntermediateNumElts = IntermediateVT.getVectorMinNumElements(); in getCopyToPartsVector()
11046 unsigned NumElts = VT.getVectorMinNumElements(); in visitVectorReverse()
H A DLegalizeIntegerTypes.cpp4927 unsigned OpNumElts = Op.getValueType().getVectorMinNumElements(); in PromoteIntOp_CONCAT_VECTORS()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp2322 Op.getOperand(0).getSimpleValueType().getVectorMinNumElements(); in LowerOperation()
3684 if (VecVT.getVectorMinNumElements() >= 8 && in lowerINSERT_SUBVECTOR()
3685 SubVecVT.getVectorMinNumElements() >= 8) { in lowerINSERT_SUBVECTOR()
3687 assert(VecVT.getVectorMinNumElements() % 8 == 0 && in lowerINSERT_SUBVECTOR()
3688 SubVecVT.getVectorMinNumElements() % 8 == 0 && in lowerINSERT_SUBVECTOR()
3692 MVT::getVectorVT(MVT::i8, SubVecVT.getVectorMinNumElements() / 8, in lowerINSERT_SUBVECTOR()
3694 VecVT = MVT::getVectorVT(MVT::i8, VecVT.getVectorMinNumElements() / 8, in lowerINSERT_SUBVECTOR()
3793 VL = DAG.getConstant(SubVecVT.getVectorMinNumElements(), DL, XLenVT); in lowerINSERT_SUBVECTOR()
3832 if (VecVT.getVectorMinNumElements() >= 8 && in lowerEXTRACT_SUBVECTOR()
3833 SubVecVT.getVectorMinNumElements() >= 8) { in lowerEXTRACT_SUBVECTOR()
[all …]
/netbsd-src/external/apache2/llvm/dist/llvm/utils/TableGen/
H A DIntrinsicEmitter.cpp381 switch (VVT.getVectorMinNumElements()) { in EncodeFixedType()
H A DCodeGenDAGPatterns.cpp633 return B.getVectorMinNumElements() < P.getVectorMinNumElements(); in EnforceVectorSubVectorTypeIs()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
H A DAArch64TargetTransformInfo.cpp568 DstTyL.first * DstTyL.second.getVectorMinNumElements(); in isWideningInstruction()
570 SrcTyL.first * SrcTyL.second.getVectorMinNumElements(); in isWideningInstruction()
H A DAArch64ISelLowering.cpp172 switch (VT.getVectorMinNumElements()) { in getPromotedVTForPredicate()
10197 } else if (Idx == InVT.getVectorMinNumElements()) { in LowerINSERT_SUBVECTOR()
13872 unsigned NumElts = N.getValueType().getVectorMinNumElements(); in isAllActivePredicate()
13879 if (N.getValueType().getVectorMinNumElements() < NumElts) in isAllActivePredicate()
13888 return N.getValueType().getVectorMinNumElements() >= NumElts; in isAllActivePredicate()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/
H A DHexagonISelLowering.cpp2104 unsigned VecLen = VT.getVectorMinNumElements(); in getPreferredVectorAction()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp15587 128 / AVT.getVectorMinNumElements())), in PerformVECREDUCE_ADDCombine()