| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/BPF/ |
| H A D | BPFMIPeephole.cpp | 107 MachineInstr *DefInsn = MRI->getVRegDef(Reg); in isCopyFrom32Def() 122 MachineInstr *PhiDef = MRI->getVRegDef(opnd.getReg()); in isPhiFrom32Def() 161 MachineInstr *DefInsn = MRI->getVRegDef(MovMI->getOperand(1).getReg()); in isMovFrom32Def() 196 MachineInstr *SllMI = MRI->getVRegDef(ShfReg); in eliminateZExtSeq() 210 MachineInstr *MovMI = MRI->getVRegDef(SllMI->getOperand(1).getReg()); in eliminateZExtSeq() 481 MI2 = MRI->getVRegDef(SrcReg); in eliminateTruncSeq() 491 DefMI = MRI->getVRegDef(SrcReg); in eliminateTruncSeq() 498 DefMI = MRI->getVRegDef(SrcReg); in eliminateTruncSeq() 524 MachineInstr *PhiDef = MRI->getVRegDef(opnd.getReg()); in eliminateTruncSeq()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/ |
| H A D | PPCMIPeephole.cpp | 164 return MRI->getVRegDef(Reg); in getVRegDefOrNull() 290 MachineInstr *Instr = MRI->getVRegDef(RegOp); in collectUnprimedAccPHIs() 335 MachineInstr *PHIInput = MRI->getVRegDef(RegOp); in convertUnprimedAccPHIs() 452 MachineInstr *RootPHI = MRI->getVRegDef(Src); in simplifyCode() 518 MachineInstr *DefMI = MRI->getVRegDef(TrueReg1); in simplifyCode() 535 MachineInstr *LoadMI = MRI->getVRegDef(FeedReg1); in simplifyCode() 628 MachineInstr *DefMI = MRI->getVRegDef(TrueReg); in simplifyCode() 638 MachineInstr *Splt = MRI->getVRegDef(ConvReg); in simplifyCode() 691 MachineInstr *DefMI = MRI->getVRegDef(TrueReg); in simplifyCode() 703 MachineInstr *P1 = MRI->getVRegDef(DefsReg1); in simplifyCode() [all …]
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| H A D | PPCBranchCoalescing.cpp | 367 MachineInstr *Op1Def = MRI->getVRegDef(Op1.getReg()); in identicalOperands() 368 MachineInstr *Op2Def = MRI->getVRegDef(Op2.getReg()); in identicalOperands() 467 MachineInstr *DefInst = MRI->getVRegDef(Use.getReg()); in canMoveToEnd()
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| H A D | PPCVSXSwapRemoval.cpp | 558 MachineInstr *MI = MRI->getVRegDef(SrcReg); in lookThruCopyLike() 618 MachineInstr* DefMI = MRI->getVRegDef(Reg); in formWebs() 723 MachineInstr *DefMI = MRI->getVRegDef(UseReg); in recordUnoptimizableWebs() 800 MachineInstr *DefMI = MRI->getVRegDef(UseReg); in markSwapsForRemoval()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARM/ |
| H A D | MLxExpansionPass.cpp | 94 MachineInstr *DefMI = MRI->getVRegDef(Reg); in getAccDefMI() 101 DefMI = MRI->getVRegDef(Reg); in getAccDefMI() 107 DefMI = MRI->getVRegDef(Reg); in getAccDefMI() 146 MachineInstr *DefMI = MRI->getVRegDef(Reg); in hasLoopHazard() 157 DefMI = MRI->getVRegDef(SrcReg); in hasLoopHazard() 165 DefMI = MRI->getVRegDef(Reg); in hasLoopHazard() 171 DefMI = MRI->getVRegDef(Reg); in hasLoopHazard()
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| H A D | A15SDOptimizer.cpp | 157 MachineInstr *MI = MRI->getVRegDef(SReg); in getPrefSPRLane() 251 MachineInstr *DPRMI = MRI->getVRegDef(MI->getOperand(1).getReg()); in optimizeSDPattern() 252 MachineInstr *SPRMI = MRI->getVRegDef(MI->getOperand(2).getReg()); in optimizeSDPattern() 303 MachineInstr *Def = MRI->getVRegDef(OpReg); in optimizeSDPattern() 346 MachineInstr *Def = MRI->getVRegDef(MI->getOperand(1).getReg()); in elideCopies() 374 MachineInstr *NewMI = MRI->getVRegDef(Reg); in elideCopiesAndPHIs() 382 MachineInstr *NewMI = MRI->getVRegDef(MI->getOperand(1).getReg()); in elideCopiesAndPHIs() 605 MachineInstr *Def = MRI->getVRegDef(*I); in runOnInstruction()
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| H A D | MVETPAndVPTOptimisationsPass.cpp | 99 MI = MRI->getVRegDef(MI->getOperand(1).getReg()); in INITIALIZE_PASS_DEPENDENCY() 148 LookThroughCOPY(MRI->getVRegDef(LoopEnd->getOperand(0).getReg()), MRI); in findLoopComponents() 157 LookThroughCOPY(MRI->getVRegDef(LoopDec->getOperand(1).getReg()), MRI); in findLoopComponents() 170 LoopStart = LookThroughCOPY(MRI->getVRegDef(StartReg), MRI); in findLoopComponents() 469 MachineInstr *Phi = LookThroughCOPY(MRI->getVRegDef(CountReg), MRI); in ConvertTailPredLoop() 898 MachineInstr *Copy = MRI->getVRegDef(VPR); in ReplaceConstByVPNOTs() 909 MachineInstr *Def = MRI->getVRegDef(GPR); in ReplaceConstByVPNOTs() 927 DeadInstructions.insert(MRI->getVRegDef(GPR)); in ReplaceConstByVPNOTs() 944 DeadInstructions.insert(MRI->getVRegDef(GPR)); in ReplaceConstByVPNOTs()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/ |
| H A D | HexagonHardwareLoops.cpp | 440 MachineInstr *DI = MRI->getVRegDef(PhiOpReg); in findInductionRegister() 448 if (MRI->getVRegDef(IndReg) == Phi && checkForImmediate(Opnd2, V)) { in findInductionRegister() 466 MachineInstr *PredI = MRI->getVRegDef(PredR); in findInductionRegister() 502 IVOp = MRI->getVRegDef(F->first); in findInductionRegister() 605 MachineInstr *IV_Phi = MRI->getVRegDef(IVReg); in getLoopTripCount() 651 MachineInstr *CondI = MRI->getVRegDef(PredReg); in getLoopTripCount() 699 MachineBasicBlock *DefBB = MRI->getVRegDef(R)->getParent(); in getLoopTripCount() 705 OldInsts.push_back(MRI->getVRegDef(R)); in getLoopTripCount() 709 MachineBasicBlock *DefBB = MRI->getVRegDef(R)->getParent(); in getLoopTripCount() 715 OldInsts.push_back(MRI->getVRegDef(R)); in getLoopTripCount() [all …]
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| H A D | HexagonVExtract.cpp | 78 MachineInstr *DI = MRI.getVRegDef(ExtIdxR); in genElemLoad() 149 MachineInstr *DefI = MRI.getVRegDef(VecR); in runOnMachineFunction() 183 MachineInstr *AlignaI = MRI.getVRegDef(AR); in runOnMachineFunction()
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| H A D | HexagonGenPredicate.cpp | 234 MachineInstr *DefI = MRI->getVRegDef(Reg.R); in processPredicateGPR() 256 MachineInstr *DefI = MRI->getVRegDef(Reg.R); in getPredRegFor() 330 const MachineInstr *DefI = MRI->getVRegDef(PR.R); in isScalarPred()
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| H A D | HexagonGenInsert.cpp | 1025 const MachineInstr *DefI = MRI->getVRegDef(R); in findRemovableRegisters() 1077 MachineInstr *DefVR = MRI->getVRegDef(VR); in pruneCoveredSets() 1156 const MachineInstr *DefV = MRI->getVRegDef(VR); in pruneUsesTooFar() 1160 const MachineInstr *DefS = MRI->getVRegDef(SR); in pruneUsesTooFar() 1161 const MachineInstr *DefI = MRI->getVRegDef(IR); in pruneUsesTooFar() 1347 const MachineInstr *DefI = MRI->getVRegDef(I->first); in selectCandidates() 1411 MachineInstr *MI = MRI->getVRegDef(I->first); in generateInserts() 1445 MachineInstr *DefI = MRI->getVRegDef(I->first); in generateInserts()
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| /netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/GlobalISel/ |
| H A D | LegalizationArtifactCombiner.h | 66 markInstAndDefDead(MI, *MRI.getVRegDef(SrcReg), DeadInsts); in tryCombineAnyExt() 84 auto *SrcMI = MRI.getVRegDef(SrcReg); in tryCombineAnyExt() 127 markInstAndDefDead(MI, *MRI.getVRegDef(SrcReg), DeadInsts); in tryCombineZExt() 139 markDefDead(MI, *MRI.getVRegDef(SrcReg), DeadInsts); in tryCombineZExt() 144 auto *SrcMI = MRI.getVRegDef(SrcReg); in tryCombineZExt() 180 markInstAndDefDead(MI, *MRI.getVRegDef(SrcReg), DeadInsts); in tryCombineSExt() 194 markInstAndDefDead(MI, *MRI.getVRegDef(SrcReg), DeadInsts); in tryCombineSExt() 199 auto *SrcMI = MRI.getVRegDef(SrcReg); in tryCombineSExt() 226 auto *SrcMI = MRI.getVRegDef(SrcReg); in tryCombineTrunc() 309 markInstAndDefDead(MI, *MRI.getVRegDef(TruncSrc), DeadInsts); in tryCombineTrunc() [all …]
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/GlobalISel/ |
| H A D | InstructionSelector.cpp | 50 MachineInstr *RootI = MRI.getVRegDef(Root.getReg()); in isBaseWithConstantOffset() 55 MachineInstr *RHSI = MRI.getVRegDef(RHS.getReg()); in isBaseWithConstantOffset()
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| H A D | Utils.cpp | 83 MachineInstr *RegDef = MRI.getVRegDef(Reg); in constrainOperandRegClass() 315 while ((MI = MRI.getVRegDef(VReg)) && !IsConstantOpcode(MI->getOpcode()) && in getConstantVRegValWithLookThrough() 370 MachineInstr *MI = MRI.getVRegDef(VReg); in getConstantIntVRegVal() 378 MachineInstr *MI = MRI.getVRegDef(VReg); in getConstantFPVRegVal() 387 auto *DefMI = MRI.getVRegDef(Reg); in getDefSrcRegIgnoringCopies() 397 DefMI = MRI.getVRegDef(SrcReg); in getDefSrcRegIgnoringCopies() 548 const MachineInstr *DefMI = MRI.getVRegDef(Val); in isKnownNeverNaN() 635 MachineInstr *Def = MRI.getVRegDef(LiveIn); in getFunctionLiveInPhysReg()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/ |
| H A D | ModuloSchedule.cpp | 399 int LoopValStage = Schedule.getStage(MRI.getVRegDef(LoopVal)); in generateExistingPhis() 450 MachineInstr *InstOp1 = MRI.getVRegDef(PhiOp1); in generateExistingPhis() 458 InstOp1 = MRI.getVRegDef(PhiOp1); in generateExistingPhis() 472 if (MachineInstr *InstOp1 = MRI.getVRegDef(PhiOp1)) in generateExistingPhis() 476 MachineInstr *PhiInst = MRI.getVRegDef(LoopVal); in generateExistingPhis() 643 if (MachineInstr *InstOp2 = MRI.getVRegDef(PhiOp2)) in generatePhis() 654 if (MachineInstr *InstOp1 = MRI.getVRegDef(PhiOp1)) { in generatePhis() 800 MachineInstr *MI = MRI.getVRegDef(LCDef); in splitLifetimes() 930 MachineInstr *BaseDef = MRI.getVRegDef(BaseReg); in computeDelta() 933 BaseDef = MRI.getVRegDef(BaseReg); in computeDelta() [all …]
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| H A D | OptimizePHIs.cpp | 116 MachineInstr *SrcMI = MRI->getVRegDef(SrcReg); in IsSingleValuePHICycle() 123 SrcMI = MRI->getVRegDef(SrcReg); in IsSingleValuePHICycle()
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| H A D | LiveVariables.cpp | 130 assert(MRI->getVRegDef(Reg) && "Register use before def!"); in HandleVirtRegUse() 165 if (MBB == MRI->getVRegDef(Reg)->getParent()) in HandleVirtRegUse() 176 MarkVirtRegAliveInBlock(VRInfo, MRI->getVRegDef(Reg)->getParent(), Pred); in HandleVirtRegUse() 591 MarkVirtRegAliveInBlock(getVarInfo(I), MRI->getVRegDef(I)->getParent(), in runOnBlock() 653 if (VirtRegInfo[Reg].Kills[j] == MRI->getVRegDef(Reg)) in runOnMachineFunction() 724 const MachineInstr *Def = MRI.getVRegDef(Reg); in isLiveIn()
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| H A D | MachineLoopInfo.cpp | 192 assert(MRI->getVRegDef(Reg) && in isLoopInvariant() 197 if (contains(MRI->getVRegDef(Reg))) in isLoopInvariant()
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| H A D | MIRVRegNamerUtils.cpp | 81 return MRI.getVRegDef(MO.getReg())->getOpcode(); in getInstructionOpcodeHash() 141 std::string Name = getInstructionOpcodeHash(*MRI.getVRegDef(VReg)); in createVirtualRegister()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64PostLegalizerCombiner.cpp | 76 MachineInstr *Other = MRI.getVRegDef(Src1Op1); in matchExtractVecEltPairwiseAdd() 79 Other = MRI.getVRegDef(Src1Op2); in matchExtractVecEltPairwiseAdd() 84 Other == MRI.getVRegDef(Shuffle->getOperand(1).getReg())) { in matchExtractVecEltPairwiseAdd() 112 unsigned Opc = MRI.getVRegDef(R)->getOpcode(); in isSignExtended() 118 return MRI.getVRegDef(R)->getOpcode() == TargetOpcode::G_ZEXT; in isZeroExtended()
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| H A D | AArch64RegisterBankInfo.cpp | 519 onlyDefinesFP(*MRI.getVRegDef(Op.getReg()), MRI, TRI, Depth + 1); in hasFPConstraints() 690 auto ScalarDef = MRI.getVRegDef(ScalarReg); in getInstrMapping() 774 MachineInstr *DefMI = MRI.getVRegDef(VReg); in getInstrMapping() 823 MachineInstr *DefMI = MRI.getVRegDef(VReg); in getInstrMapping() 903 MachineInstr *DefMI = MRI.getVRegDef(VReg); in getInstrMapping() 907 return Op.isDef() || MRI.getVRegDef(Op.getReg())->getOpcode() == in getInstrMapping()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/WebAssembly/ |
| H A D | WebAssemblyFixBrTableDefaults.cpp | 61 auto ExtMI = MF.getRegInfo().getVRegDef(MI.getOperand(0).getReg()); in fixBrTableIndex() 123 auto *RangeCheck = MRI.getVRegDef(Cond[1].getReg()); in fixBrTableDefault()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
| H A D | SIFoldOperands.cpp | 500 MachineInstr *Def = MRI.getVRegDef(UseReg); in getRegSeqInit() 508 for (MachineInstr *SubDef = MRI.getVRegDef(Sub->getReg()); in getRegSeqInit() 511 SubDef = MRI.getVRegDef(Sub->getReg())) { in getRegSeqInit() 565 MachineInstr *Def = MRI.getVRegDef(UseReg); in tryToFoldACImm() 1035 MachineInstr *Def = MRI.getVRegDef(Op.getReg()); in getImmOrMaterializedImm() 1353 MachineInstr *Def = MRI->getVRegDef(ClampSrc->getReg()); in tryFoldClamp() 1492 MachineInstr *Def = MRI->getVRegDef(RegOp->getReg()); in tryFoldOMod() 1531 const MachineInstr *SubDef = MRI->getVRegDef(Op->getReg()); in tryFoldRegSequence() 1576 MachineInstr *SubDef = MRI->getVRegDef(Def->getReg()); in tryFoldRegSequence() 1624 MachineInstr *Copy = MRI->getVRegDef(PhiIn); in tryFoldLCSSAPhi() [all …]
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| H A D | SIFixSGPRCopies.cpp | 625 MachineInstr *DefMI = MRI->getVRegDef(SrcReg); in runOnMachineFunction() 736 MachineInstr *DefMI = MRI->getVRegDef(MO->getReg()); in runOnMachineFunction() 827 MachineInstr *DefMI = MRI->getVRegDef(MI.getOperand(I).getReg()); in processPHINode() 836 MachineInstr *Def = MRI->getVRegDef(InputReg); in processPHINode() 851 MachineInstr *SrcDef = MRI->getVRegDef(SrcReg); in processPHINode()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/ |
| H A D | RISCVMergeBaseOffset.cpp | 146 MachineInstr &OffsetTail = *MRI->getVRegDef(Reg); in matchLargeOffset() 155 *MRI->getVRegDef(OffsetTail.getOperand(1).getReg()); in matchLargeOffset()
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