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Searched refs:getVGPRClassForBitWidth (Results 1 – 4 of 4) sorted by relevance

/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
H A DSIRegisterInfo.cpp1910 SIRegisterInfo::getVGPRClassForBitWidth(unsigned BitWidth) const { in getVGPRClassForBitWidth() function in SIRegisterInfo
2085 const TargetRegisterClass *VRC = getVGPRClassForBitWidth(Size); in hasVGPRs()
2099 assert(getVGPRClassForBitWidth(Size) && "Invalid register class size"); in hasAGPRs()
2108 const TargetRegisterClass *VRC = getVGPRClassForBitWidth(Size); in getEquivalentVGPRClass()
2146 RC = getVGPRClassForBitWidth(Size); in getSubRegClass()
2331 return getVGPRClassForBitWidth(std::max(32u, Size)); in getRegClassForSizeOnBank()
2458 return RC.hasSuperClassEq(getVGPRClassForBitWidth(getRegSizeInBits(RC))); in isProperlyAlignedRC()
H A DSIRegisterInfo.h141 const TargetRegisterClass *getVGPRClassForBitWidth(unsigned BitWidth) const;
H A DSIISelLowering.cpp93 addRegisterClass(MVT::v3f32, TRI->getVGPRClassForBitWidth(96)); in SITargetLowering()
99 addRegisterClass(MVT::v4f32, TRI->getVGPRClassForBitWidth(128)); in SITargetLowering()
102 addRegisterClass(MVT::v5f32, TRI->getVGPRClassForBitWidth(160)); in SITargetLowering()
105 addRegisterClass(MVT::v8f32, TRI->getVGPRClassForBitWidth(256)); in SITargetLowering()
108 addRegisterClass(MVT::v4f64, TRI->getVGPRClassForBitWidth(256)); in SITargetLowering()
111 addRegisterClass(MVT::v16f32, TRI->getVGPRClassForBitWidth(512)); in SITargetLowering()
114 addRegisterClass(MVT::v8f64, TRI->getVGPRClassForBitWidth(512)); in SITargetLowering()
117 addRegisterClass(MVT::v16f64, TRI->getVGPRClassForBitWidth(1024)); in SITargetLowering()
131 addRegisterClass(MVT::v32f32, TRI->getVGPRClassForBitWidth(1024)); in SITargetLowering()
11534 RC = TRI->getVGPRClassForBitWidth(BitWidth); in getRegForInlineAsmConstraint()
H A DSILoadStoreOptimizer.cpp1597 : TRI->getVGPRClassForBitWidth(BitWidth); in getTargetRegisterClass()