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Searched refs:getSubReg (Results 1 – 25 of 140) sorted by relevance

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/netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/
H A DPeepholeOptimizer.cpp514 if (UseSrcSubIdx && UseMO.getSubReg() != SubIdx) in INITIALIZE_PASS_DEPENDENCY()
851 Src = RegSubRegPair(MOSrc.getReg(), MOSrc.getSubReg()); in getNextRewritableSource()
854 Dst = RegSubRegPair(MODef.getReg(), MODef.getSubReg()); in getNextRewritableSource()
897 Dst = RegSubRegPair(MODef.getReg(), MODef.getSubReg()); in getNextRewritableSource()
934 Src = RegSubRegPair(MOInsertedReg.getReg(), MOInsertedReg.getSubReg()); in getNextRewritableSource()
939 if (MODef.getSubReg()) in getNextRewritableSource()
982 if (MOExtractedReg.getSubReg()) in getNextRewritableSource()
990 Dst = RegSubRegPair(MODef.getReg(), MODef.getSubReg()); in getNextRewritableSource()
1059 if ((Src.SubReg = MOInsertedReg.getSubReg())) in getNextRewritableSource()
1069 return MODef.getSubReg() == 0; in getNextRewritableSource()
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H A DDetectDeadLanes.cpp159 unsigned SrcSubIdx = MO.getSubReg(); in isCrossCopy()
198 unsigned MOSubReg = MO.getSubReg(); in addUsedLanesOnOperand()
294 TRI->reverseComposeSubRegIndexLaneMask(Use.getSubReg(), DefinedLanes); in transferDefinedLanesStep()
343 assert(Def.getSubReg() == 0 && in transferDefinedLanes()
395 unsigned MOSubReg = MO.getSubReg(); in determineInitialDefinedLanes()
409 assert(Def.getSubReg() == 0 && in determineInitialDefinedLanes()
424 unsigned SubReg = MO.getSubReg(); in determineInitialUsedLanes()
457 unsigned SubReg = MO.getSubReg(); in isUndefRegAtInput()
H A DCalcSpillWeights.cpp52 Sub = MI->getOperand(0).getSubReg(); in copyHint()
54 HSub = MI->getOperand(1).getSubReg(); in copyHint()
56 Sub = MI->getOperand(1).getSubReg(); in copyHint()
58 HSub = MI->getOperand(0).getSubReg(); in copyHint()
68 MCRegister CopiedPReg = HSub ? TRI.getSubReg(HReg, HSub) : HReg.asMCReg(); in copyHint()
H A DTargetInstrInfo.cpp187 unsigned SubReg0 = HasDef ? MI.getOperand(0).getSubReg() : 0; in commuteInstructionImpl()
188 unsigned SubReg1 = MI.getOperand(Idx1).getSubReg(); in commuteInstructionImpl()
189 unsigned SubReg2 = MI.getOperand(Idx2).getSubReg(); in commuteInstructionImpl()
454 if (FoldOp.getSubReg() || LiveOp.getSubReg()) in canFoldCopy()
540 TII.getStackSlotRange(RC, MO.getSubReg(), SpillSize, SpillOffset, MF); in foldPatchpoint()
586 if (auto SubReg = MI.getOperand(OpIdx).getSubReg()) { in foldMemoryOperand()
932 if (Register::isVirtualRegister(DefReg) && MI.getOperand(0).getSubReg() && in isReallyTriviallyReMaterializableGeneric()
1304 InputRegs.push_back(RegSubRegPairAndIdx(MOReg.getReg(), MOReg.getSubReg(), in getRegSequenceInputs()
1330 InputReg.SubReg = MOReg.getSubReg(); in getExtractSubregInputs()
1355 BaseReg.SubReg = MOBaseReg.getSubReg(); in getInsertSubregInputs()
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H A DRegAllocFast.cpp835 unsigned SubRegIdx = MO.getSubReg(); in allocVirtRegUndef()
837 PhysReg = TRI->getSubReg(PhysReg, SubRegIdx); in allocVirtRegUndef()
866 if (MO.getSubReg() && !MO.isUndef()) { in defineLiveThroughVirtReg()
953 if (MI.isCopy() && MI.getOperand(1).getSubReg() == 0) { in useVirtReg()
981 if (!MO.getSubReg()) { in setPhysReg()
988 MO.setReg(PhysReg ? TRI->getSubReg(PhysReg, MO.getSubReg()) : MCRegister()); in setPhysReg()
1123 if (MO.isTied() || (MO.getSubReg() != 0 && !MO.isUndef())) in allocateInstruction()
1207 (MO0.getSubReg() == 0 && !MO0.isUndef()); in allocateInstruction()
1209 (MO1.getSubReg() == 0 && !MO1.isUndef()); in allocateInstruction()
1224 (MO.getSubReg() && !MO.isUndef())) { in allocateInstruction()
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H A DMachineOperand.cpp80 if (SubIdx && getSubReg()) in substVirtReg()
81 SubIdx = TRI.composeSubRegIndices(SubIdx, getSubReg()); in substVirtReg()
89 if (getSubReg()) { in substPhysReg()
90 Reg = TRI.getSubReg(Reg, getSubReg()); in substPhysReg()
290 getSubReg() == Other.getSubReg(); in isIdenticalTo()
355 return hash_combine(MO.getType(), (unsigned)MO.getReg(), MO.getSubReg(), MO.isDef()); in hash_value()
773 if (unsigned SubReg = getSubReg()) { in print()
H A DTargetRegisterInfo.cpp310 if (RCI.getSubReg() == Idx) in getMatchingSuperRegClass()
349 unsigned FinalA = composeSubRegIndices(IA.getSubReg(), SubA); in getCommonSuperRegClass()
358 unsigned FinalB = composeSubRegIndices(IB.getSubReg(), SubB); in getCommonSuperRegClass()
368 *BestPreA = IA.getSubReg(); in getCommonSuperRegClass()
369 *BestPreB = IB.getSubReg(); in getCommonSuperRegClass()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/SystemZ/
H A DSystemZRegisterInfo.cpp33 MO.getSubReg() == SystemZ::subreg_l32 || in getRC32()
34 MO.getSubReg() == SystemZ::subreg_hl32) in getRC32()
37 MO.getSubReg() == SystemZ::subreg_h32 || in getRC32()
38 MO.getSubReg() == SystemZ::subreg_hh32) in getRC32()
114 if (MO->getSubReg()) in getRegAllocationHints()
115 PhysReg = getSubReg(PhysReg, MO->getSubReg()); in getRegAllocationHints()
116 if (VRRegMO->getSubReg()) in getRegAllocationHints()
117 PhysReg = getMatchingSuperReg(PhysReg, VRRegMO->getSubReg(), in getRegAllocationHints()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
H A DSIFoldOperands.cpp318 Old.substVirtReg(New->getReg(), New->getSubReg(), TRI); in updateOperand()
510 !Sub->getSubReg() && TII->isFoldableCopy(*SubDef); in getRegSeqInit()
567 if (!UseOp.getSubReg() && Def && TII->isFoldableCopy(*Def)) { in tryToFoldACImm()
616 if (UseOp.isImplicit() || UseOp.getSubReg() != AMDGPU::NoSubRegister) in foldOperand()
634 if (RSUse.getSubReg() != RegSeqDstSubReg) in foldOperand()
740 !UseMI->getOperand(1).getSubReg()) { in foldOperand()
745 UseMI->getOperand(1).setSubReg(OpToFold.getSubReg()); in foldOperand()
883 UseMI->getOperand(1).setSubReg(OpToFold.getSubReg()); in foldOperand()
915 if (UseOp.getSubReg() && AMDGPU::getRegBitWidth(FoldRC->getID()) == 64) { in foldOperand()
923 if (UseOp.getSubReg() == AMDGPU::sub0) { in foldOperand()
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H A DR600ExpandSpecialInstrs.cpp211 Src0 = TRI.getSubReg(Src0, SubRegIndex); in runOnMachineFunction()
212 Src1 = TRI.getSubReg(Src1, SubRegIndex); in runOnMachineFunction()
217 Src1 = TRI.getSubReg(Src0, SubRegIndex1); in runOnMachineFunction()
218 Src0 = TRI.getSubReg(Src0, SubRegIndex0); in runOnMachineFunction()
226 DstReg = TRI.getSubReg(DstReg, SubRegIndex); in runOnMachineFunction()
H A DSIFrameLowering.cpp166 Register TargetLo = TRI->getSubReg(TargetReg, AMDGPU::sub0); in buildGitPtr()
167 Register TargetHi = TRI->getSubReg(TargetReg, AMDGPU::sub1); in buildGitPtr()
229 FlatScrInitLo = TRI->getSubReg(FlatScrInit, AMDGPU::sub0); in emitEntryFunctionFlatScratchInit()
230 FlatScrInitHi = TRI->getSubReg(FlatScrInit, AMDGPU::sub1); in emitEntryFunctionFlatScratchInit()
267 FlatScrInitLo = TRI->getSubReg(FlatScratchInitReg, AMDGPU::sub0); in emitEntryFunctionFlatScratchInit()
268 FlatScrInitHi = TRI->getSubReg(FlatScratchInitReg, AMDGPU::sub1); in emitEntryFunctionFlatScratchInit()
528 Register Rsrc01 = TRI->getSubReg(ScratchRsrcReg, AMDGPU::sub0_sub1); in emitEntryFunctionScratchRsrcRegSetup()
529 Register Rsrc03 = TRI->getSubReg(ScratchRsrcReg, AMDGPU::sub3); in emitEntryFunctionScratchRsrcRegSetup()
569 Register Rsrc2 = TRI->getSubReg(ScratchRsrcReg, AMDGPU::sub2); in emitEntryFunctionScratchRsrcRegSetup()
570 Register Rsrc3 = TRI->getSubReg(ScratchRsrcReg, AMDGPU::sub3); in emitEntryFunctionScratchRsrcRegSetup()
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H A DSIShrinkInstructions.cpp400 TRI.getSubRegIndexLaneMask(MO.getSubReg()); in instAccessReg()
425 Reg = TRI.getSubReg(Reg, TRI.getSubRegFromChannel(I)); in getSubRegForIndex()
474 unsigned Tsub = MovT.getOperand(0).getSubReg(); in matchSwap()
480 unsigned Xsub = Xop.getSubReg(); in matchSwap()
505 MovY->getOperand(1).getSubReg() != Tsub || in matchSwap()
510 unsigned Ysub = MovY->getOperand(0).getSubReg(); in matchSwap()
536 I->getOperand(0).getSubReg() != Xsub) { in matchSwap()
H A DSIOptimizeExecMaskingPreRA.cpp140 unsigned CmpSubReg = AndCC->getSubReg(); in optimizeVcndVcmpPair()
144 CmpSubReg = AndCC->getSubReg(); in optimizeVcndVcmpPair()
163 auto *Sel = TRI->findReachingDef(SelReg, Op1->getSubReg(), *Cmp, *MRI, LIS); in optimizeVcndVcmpPair()
193 .addReg(CCReg, getUndefRegState(CC->isUndef()), CC->getSubReg()); in optimizeVcndVcmpPair()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/VE/
H A DVERegisterInfo.cpp166 Register SrcHiReg = getSubReg(SrcReg, VE::sub_even); in eliminateFrameIndex()
167 Register SrcLoReg = getSubReg(SrcReg, VE::sub_odd); in eliminateFrameIndex()
181 Register DestHiReg = getSubReg(DestReg, VE::sub_even); in eliminateFrameIndex()
182 Register DestLoReg = getSubReg(DestReg, VE::sub_odd); in eliminateFrameIndex()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/
H A DHexagonSplitDouble.cpp259 if (&MO == &Op || !MO.isReg() || MO.getSubReg()) in partitionRegisters()
320 if (!Op.getSubReg()) in profit()
324 if (MI->getOperand(1).getSubReg() != 0) in profit()
443 if (Op.getSubReg()) in isProfitable()
603 unsigned SR = Op.getSubReg(); in createHalfInstr()
649 .addReg(AdrOp.getReg(), RSA & ~RegState::Kill, AdrOp.getSubReg()) in splitMemRef()
652 .addReg(AdrOp.getReg(), RSA & ~RegState::Kill, AdrOp.getSubReg()) in splitMemRef()
658 .addReg(AdrOp.getReg(), RSA & ~RegState::Kill, AdrOp.getSubReg()) in splitMemRef()
662 .addReg(AdrOp.getReg(), RSA & ~RegState::Kill, AdrOp.getSubReg()) in splitMemRef()
674 assert(!UpdOp.getSubReg() && "Def operand with subreg"); in splitMemRef()
[all …]
H A DHexagonRDFOpt.cpp124 assert(DstOp.getSubReg() == 0 && "Unexpected subregister"); in INITIALIZE_PASS_DEPENDENCY()
126 DFG.makeRegRef(HiOp.getReg(), HiOp.getSubReg())); in INITIALIZE_PASS_DEPENDENCY()
128 DFG.makeRegRef(LoOp.getReg(), LoOp.getSubReg())); in INITIALIZE_PASS_DEPENDENCY()
140 mapRegs(DFG.makeRegRef(DstOp.getReg(), DstOp.getSubReg()), in INITIALIZE_PASS_DEPENDENCY()
141 DFG.makeRegRef(SrcOp.getReg(), SrcOp.getSubReg())); in INITIALIZE_PASS_DEPENDENCY()
H A DHexagonAsmPrinter.cpp136 RegNumber = TRI->getSubReg(RegNumber, ExtraCode[0] == 'L' ? in PrintAsmOperand()
463 unsigned High = RI->getSubReg(MO1.getReg(), Hexagon::isub_hi); in HexagonProcessInstruction()
464 unsigned Low = RI->getSubReg(MO1.getReg(), Hexagon::isub_lo); in HexagonProcessInstruction()
540 unsigned High = RI->getSubReg(MO.getReg(), Hexagon::isub_hi); in HexagonProcessInstruction()
541 unsigned Low = RI->getSubReg(MO.getReg(), Hexagon::isub_lo); in HexagonProcessInstruction()
552 unsigned High = RI->getSubReg(MO.getReg(), Hexagon::isub_hi); in HexagonProcessInstruction()
553 unsigned Low = RI->getSubReg(MO.getReg(), Hexagon::isub_lo); in HexagonProcessInstruction()
566 unsigned High = RI->getSubReg(MO.getReg(), Hexagon::isub_hi); in HexagonProcessInstruction()
567 unsigned Low = RI->getSubReg(MO.getReg(), Hexagon::isub_lo); in HexagonProcessInstruction()
H A DHexagonInstrInfo.cpp133 return isIntRegForSubInst(HRI.getSubReg(Reg, Hexagon::isub_lo)) && in isDblRegForSubInst()
134 isIntRegForSubInst(HRI.getSubReg(Reg, Hexagon::isub_hi)); in isDblRegForSubInst()
879 Register SrcLo = HRI.getSubReg(SrcReg, Hexagon::vsub_lo); in copyPhysReg()
880 Register SrcHi = HRI.getSubReg(SrcReg, Hexagon::vsub_hi); in copyPhysReg()
1054 Register SrcLo = HRI.getSubReg(SrcReg, Hexagon::vsub_lo); in expandPostRAPseudo()
1055 Register SrcHi = HRI.getSubReg(SrcReg, Hexagon::vsub_hi); in expandPostRAPseudo()
1069 Register SrcSubLo = HRI.getSubReg(SrcReg, Hexagon::vsub_lo); in expandPostRAPseudo()
1078 Register SrcSubHi = HRI.getSubReg(SrcReg, Hexagon::vsub_hi); in expandPostRAPseudo()
1087 assert(BaseOp.getSubReg() == 0); in expandPostRAPseudo()
1102 assert(BaseOp.getSubReg() == 0); in expandPostRAPseudo()
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H A DHexagonExpandCondsets.cpp180 Sub(Op.getSubReg()) {} in RegisterRef()
325 LaneBitmask SLM = getLaneMask(Reg, Op.getSubReg()); in updateKillFlags()
377 Register DR = Op.getReg(), DSR = Op.getSubReg(); in updateDeadsInRange()
594 MCRegister PhysS = (RS.Sub == 0) ? PhysR : TRI->getSubReg(PhysR, RS.Sub); in getCondTfrOpcode()
649 .addReg(PredOp.getReg(), PredState, PredOp.getSubReg()) in genCondTfrFor()
650 .addReg(SrcOp.getReg(), SrcState, SrcOp.getSubReg()); in genCondTfrFor()
654 .addReg(PredOp.getReg(), PredState, PredOp.getSubReg()) in genCondTfrFor()
676 Register DR = MD.getReg(), DSR = MD.getSubReg(); in split()
886 MB.addReg(DefOp.getReg(), getRegState(DefOp), DefOp.getSubReg()); in predicateAt()
888 PredOp.getSubReg()); in predicateAt()
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H A DHexagonSplitConst32AndConst64.cpp89 Register DestLo = TRI->getSubReg(DestReg, Hexagon::isub_lo); in runOnMachineFunction()
90 Register DestHi = TRI->getSubReg(DestReg, Hexagon::isub_hi); in runOnMachineFunction()
H A DRDFCopy.cpp46 RegisterRef DstR = DFG.makeRegRef(Dst.getReg(), Dst.getSubReg()); in interpretAsCopy()
47 RegisterRef SrcR = DFG.makeRegRef(Src.getReg(), Src.getSubReg()); in interpretAsCopy()
128 return S.getSubReg(); in run()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
H A DAArch64AdvSIMDScalarPass.cpp144 if (isFPR64(MI->getOperand(0).getReg(), MI->getOperand(0).getSubReg(), in getSrcFromCopy()
146 isGPR64(MI->getOperand(1).getReg(), MI->getOperand(1).getSubReg(), MRI)) in getSrcFromCopy()
148 if (isGPR64(MI->getOperand(0).getReg(), MI->getOperand(0).getSubReg(), in getSrcFromCopy()
150 isFPR64(MI->getOperand(1).getReg(), MI->getOperand(1).getSubReg(), in getSrcFromCopy()
152 SubReg = MI->getOperand(1).getSubReg(); in getSrcFromCopy()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Sparc/
H A DSparcRegisterInfo.cpp186 Register SrcEvenReg = getSubReg(SrcReg, SP::sub_even64); in eliminateFrameIndex()
187 Register SrcOddReg = getSubReg(SrcReg, SP::sub_odd64); in eliminateFrameIndex()
198 Register DestEvenReg = getSubReg(DestReg, SP::sub_even64); in eliminateFrameIndex()
199 Register DestOddReg = getSubReg(DestReg, SP::sub_odd64); in eliminateFrameIndex()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
H A DARMExpandPseudoInsts.cpp497 D0 = TRI->getSubReg(Reg, ARM::dsub_0); in GetDSubRegs()
498 D1 = TRI->getSubReg(Reg, ARM::dsub_1); in GetDSubRegs()
499 D2 = TRI->getSubReg(Reg, ARM::dsub_2); in GetDSubRegs()
500 D3 = TRI->getSubReg(Reg, ARM::dsub_3); in GetDSubRegs()
502 D0 = TRI->getSubReg(Reg, ARM::dsub_4); in GetDSubRegs()
503 D1 = TRI->getSubReg(Reg, ARM::dsub_5); in GetDSubRegs()
504 D2 = TRI->getSubReg(Reg, ARM::dsub_6); in GetDSubRegs()
505 D3 = TRI->getSubReg(Reg, ARM::dsub_7); in GetDSubRegs()
507 D0 = TRI->getSubReg(Reg, ARM::dsub_3); in GetDSubRegs()
508 D1 = TRI->getSubReg(Reg, ARM::dsub_4); in GetDSubRegs()
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/MC/
H A DMCRegisterInfo.cpp27 if (RC->contains(*Supers) && Reg == getSubReg(*Supers, SubIdx)) in getMatchingSuperReg()
32 MCRegister MCRegisterInfo::getSubReg(MCRegister Reg, unsigned Idx) const { in getSubReg() function in MCRegisterInfo

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