Searched refs:getStage (Results 1 – 3 of 3) sorted by relevance
26 OS << "[stage " << getStage(MI) << " @" << getCycle(MI) << "c] " << *MI; in print()75 int DefStage = Schedule.getStage(MI); in expand()89 int UseStage = Schedule.getStage(UseMI); in expand()135 unsigned StageNum = Schedule.getStage(CI); in generatePipelinedLoop()216 if (Schedule.getStage(&*BBI) == StageNum) { in generateProlog()294 if ((unsigned)Schedule.getStage(In) == StageNum) { in generateEpilog()398 int StageScheduled = Schedule.getStage(&*BBI); in generateExistingPhis()399 int LoopValStage = Schedule.getStage(MRI.getVRegDef(LoopVal)); in generateExistingPhis()453 int PhiStage = Schedule.getStage(InstOp1); in generateExistingPhis()459 int PhiOpStage = Schedule.getStage(InstOp1); in generateExistingPhis()[all …]
251 LiveRangeStage getStage(const LiveInterval &VirtReg) const { in getStage() function in __anone1e285680111::RAGreedy894 bool CanSplit = getStage(B) < RS_Spill; in shouldEvict()956 if (getStage(*Intf) == RS_Done) in canEvictInterference()1035 if (getStage(*Intf) == RS_Done) in canEvictInterferenceInRange()1806 if (getStage(Reg) != RS_New) in splitAroundRegion()2056 if (getStage(LI) == RS_New && IntvMap[I] == 0) in tryBlockSplit()2313 bool ProgressRequired = getStage(VirtReg) >= RS_Split2; in tryLocalSplit()2471 if (getStage(VirtReg) >= RS_Spill) in trySplit()2504 if (getStage(VirtReg) < RS_Split2) { in trySplit()2555 if (((getStage(*Intf) == RS_Done && in mayRecolorAllInterferences()[all …]
133 int getStage(MachineInstr *MI) { in getStage() function357 unsigned getStage(MachineInstr *MI) { in getStage() function360 return Schedule.getStage(MI); in getStage()