| /netbsd-src/external/apache2/llvm/dist/llvm/tools/llvm-exegesis/lib/ |
| H A D | SchedClassResolution.cpp | 53 const auto &SM = STI.getSchedModel(); in getNonRedundantWriteProcRes()
210 SCDesc(STI.getSchedModel().getSchedClassDesc(ResolvedSchedClassId)), in ResolvedSchedClass()
214 STI.getSchedModel(), NonRedundantWriteProcRes)) { in ResolvedSchedClass()
223 const auto &SM = STI.getSchedModel(); in ResolveVariantSchedClassId()
236 const bool WasVariant = SchedClassId && SubtargetInfo.getSchedModel() in resolveSchedClassId()
252 const auto &SchedModel = STI.getSchedModel(); in findProcResIdx()
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| H A D | Analysis.cpp | 142 SubtargetInfo_->getSchedModel().getSchedClassDesc(SchedClassId); in printInstructionRowCsv()
383 const auto &SM = SubtargetInfo_->getSchedModel(); in printSchedClassDescHtml()
419 writeEscaped<kEscapeHtml>(OS, SubtargetInfo_->getSchedModel() in printSchedClassDescHtml()
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| /netbsd-src/external/apache2/llvm/dist/llvm/tools/llvm-mca/Views/ |
| H A D | RegisterFileStatistics.cpp | 22 const MCSchedModel &SM = STI.getSchedModel(); in RegisterFileStatistics()
121 assert(STI.getSchedModel().hasExtraProcessorInfo() && in printView()
124 STI.getSchedModel().getExtraProcessorInfo(); in printView()
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| H A D | ResourcePressureView.cpp | 27 const MCSchedModel &SM = getSubTargetInfo().getSchedModel(); in ResourcePressureView()
109 const MCSchedModel &SM = getSubTargetInfo().getSchedModel(); in printResourcePressurePerIter()
153 printColumnNames(FOS, getSubTargetInfo().getSchedModel()); in printResourcePressurePerInst()
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| H A D | SchedulerStatistics.cpp | 22 : SM(STI.getSchedModel()), LQResourceID(0), SQResourceID(0), NumIssued(0), in SchedulerStatistics()
25 Usage(STI.getSchedModel().NumProcResourceKinds, {0, 0, 0}) { in SchedulerStatistics()
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| H A D | InstructionView.cpp | 40 const MCSchedModel &SM = STI.getSchedModel(); in toJSON()
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| H A D | TimelineView.cpp | 46 const MCSchedModel &SM = getSubTargetInfo().getSchedModel(); in onReservedBuffers()
170 getSubTargetInfo().getSchedModel().MicroOpBufferSize); in printWaitTimeEntry()
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| H A D | InstructionInfoView.cpp | 95 const MCSchedModel &SM = STI.getSchedModel(); in collectData()
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| H A D | BottleneckAnalysis.cpp | 446 : InstructionView(sti, Printer, S), Tracker(sti.getSchedModel()), in BottleneckAnalysis()
613 const MCSchedModel &SM = getSubTargetInfo().getSchedModel(); in printBottleneckHints()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/MCA/ |
| H A D | InstrBuilder.cpp | 33 const MCSchedModel &SM = STI.getSchedModel(); in InstrBuilder()
35 computeProcResourceMasks(STI.getSchedModel(), ProcResourceMasks); in InstrBuilder()
42 const MCSchedModel &SM = STI.getSchedModel(); in initializeUsedResources()
253 const MCSchedModel &SM = STI.getSchedModel(); in populateWrites()
512 assert(STI.getSchedModel().hasInstrSchedModel() && in createInstrDescImpl()
518 const MCSchedModel &SM = STI.getSchedModel(); in createInstrDescImpl()
627 unsigned ProcID = STI.getSchedModel().getProcessorID(); in createInstruction()
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| H A D | Context.cpp | 33 const MCSchedModel &SM = STI.getSchedModel(); in createDefaultPipeline()
73 const MCSchedModel &SM = STI.getSchedModel(); in createInOrderPipeline()
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| /netbsd-src/external/apache2/llvm/dist/llvm/tools/llvm-mca/ |
| H A D | llvm-mca.cpp | 344 bool IsOutOfOrder = STI->getSchedModel().isOutOfOrder(); in main()
350 if (!STI->getSchedModel().hasInstrSchedModel()) { in main()
356 if (STI->getSchedModel().InstrItineraries) in main()
460 const MCSchedModel &SM = STI->getSchedModel(); in main()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/ |
| H A D | TargetSubtargetInfo.cpp | 53 return getSchedModel().PostRAScheduler; in enablePostRAScheduler()
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| H A D | TargetSchedule.cpp | 65 SchedModel = TSInfo->getSchedModel(); in init()
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| H A D | MachinePipeliner.cpp | 1013 if (STI && STI->getSchedModel().hasInstrSchedModel()) { in minFuncUnits()
1015 STI->getSchedModel().getSchedClassDesc(SchedClass); in minFuncUnits()
1027 STI->getSchedModel().getProcResource(PRE.ProcResourceIdx); in minFuncUnits()
1056 if (STI && STI->getSchedModel().hasInstrSchedModel()) { in calcCriticalResources()
1058 STI->getSchedModel().getSchedClassDesc(SchedClass); in calcCriticalResources()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/ |
| H A D | HexagonMachineScheduler.cpp | 255 SchedModel = DAG->getSchedModel(); in initialize()
262 const InstrItineraryData *Itin = DAG->getSchedModel()->getInstrItineraries(); in initialize()
272 Top.ResourceModel = new VLIWResourceModel(STI, DAG->getSchedModel()); in initialize()
273 Bot.ResourceModel = new VLIWResourceModel(STI, DAG->getSchedModel()); in initialize()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/MC/ |
| H A D | MCSchedule.cpp | 91 const MCSchedModel &SM = STI.getSchedModel(); in getReciprocalThroughput()
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| H A D | MCSubtargetInfo.cpp | 334 InstrItins = InstrItineraryData(getSchedModel(), Stages, OperandCycles, in initInstrItins()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/MCA/Stages/ |
| H A D | DispatchStage.cpp | 35 DispatchWidth = Subtarget.getSchedModel().IssueWidth; in DispatchStage()
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| /netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/MC/ |
| H A D | MCSubtargetInfo.h | 162 const MCSchedModel &getSchedModel() const { return *CPUSchedModel; } in getSchedModel() function
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/ |
| H A D | PPCSubtarget.cpp | 192 return getSchedModel().hasInstrSchedModel() && EnableMachinePipeliner; in enableMachinePipeliner()
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| /netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/ |
| H A D | ScheduleDAGInstrs.h | 262 const TargetSchedModel *getSchedModel() const { return &SchedModel; } in getSchedModel() function
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/MCA/HardwareUnits/ |
| H A D | RegisterFile.cpp | 479 const MCSchedModel &SM = STI.getSchedModel(); in collectWrites()
559 const MCSchedModel &SM = STI.getSchedModel(); in addRegisterRead()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/MCTargetDesc/ |
| H A D | HexagonMCInstrInfo.cpp | 427 const InstrItinerary *II = STI.getSchedModel().InstrItineraries; in getCVIResources()
446 const InstrItinerary *II = STI.getSchedModel().InstrItineraries; in getUnits()
457 const InstrItinerary *II = STI.getSchedModel().InstrItineraries; in getOtherReservedSlots()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/MC/MCDisassembler/ |
| H A D | Disassembler.cpp | 198 const MCSchedModel SCModel = STI->getSchedModel(); in getLatency()
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