Searched refs:getRegClasses (Results 1 – 7 of 7) sorted by relevance
183 for (const auto &PossibleSubclass : RegisterClassHierarchy.getRegClasses()) { in visitRegisterBankClasses()200 BitVector BV(RegisterClassHierarchy.getRegClasses().size()); in visitRegisterBankClasses()221 (RegisterClassHierarchy.getRegClasses().size() + 31) / 32); in emitBaseClassImplementation()253 << RegisterClassHierarchy.getRegClasses().size() << ");\n"; in emitBaseClassImplementation()305 for (const auto &Class : RegisterClassHierarchy.getRegClasses()) { in run()
135 const auto &RegisterClasses = Bank.getRegClasses(); in runEnums()210 unsigned NumRCs = RegBank.getRegClasses().size(); in EmitRegUnitPressure()217 for (const auto &RC : RegBank.getRegClasses()) { in EmitRegUnitPressure()1033 const auto &RegisterClasses = RegBank.getRegClasses(); in runMCDesc()1184 const auto &RegisterClasses = RegBank.getRegClasses(); in runTargetHeader()1220 const auto &RegisterClasses = RegBank.getRegClasses(); in runTargetDesc()1673 for (const CodeGenRegisterClass &RC : RegBank.getRegClasses()) { in debugDump()1692 for (const CodeGenRegisterClass &SRC : RegBank.getRegClasses()) { in debugDump()
282 auto &RegClasses = RegBank->getRegClasses(); in getRegNamespace()347 auto &RegClasses = RegBank.getRegClasses(); in getSuperRegForSubReg()405 for (const auto &RC : getRegBank().getRegClasses()) { in getRegisterVTs()420 for (const auto &RC : getRegBank().getRegClasses()) in ReadLegalValueTypes()
715 std::list<CodeGenRegisterClass> &getRegClasses() { return RegClasses; } in getRegClasses() function717 const std::list<CodeGenRegisterClass> &getRegClasses() const { in getRegClasses() function
940 auto &RegClasses = RegBank.getRegClasses(); in computeSubClasses()1003 auto &RegClasses = RegBank.getRegClasses(); in getMatchingSubClassWithSubRegs()1605 for (auto &RegClass : RegBank.getRegClasses()) { in computeUberSets()1889 auto &RegClasses = getRegClasses(); in computeRegUnitSets()2342 for (const auto &RC : getRegClasses()) { in getRegClassForRegister()2383 for (const auto &RC : getRegClasses()) { in getMinimalPhysRegClass()
29 for (const auto &RC : T.getRegBank().getRegClasses()) { in getRegisterValueType()
1213 auto &RegClassList = Target.getRegBank().getRegClasses(); in buildRegisterClasses()