Searched refs:getRegClassForReg (Results 1 – 7 of 7) sorted by relevance
| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
| H A D | SIRegisterInfo.h | 227 const TargetRegisterClass *getRegClassForReg(const MachineRegisterInfo &MRI,
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| H A D | SILoadStoreOptimizer.cpp | 874 return TRI->getRegClassForReg(*MRI, Dst->getReg()); in getDataRegClass()
877 return TRI->getRegClassForReg(*MRI, Src->getReg()); in getDataRegClass()
880 return TRI->getRegClassForReg(*MRI, Src->getReg()); in getDataRegClass()
883 return TRI->getRegClassForReg(*MRI, Dst->getReg()); in getDataRegClass()
886 return TRI->getRegClassForReg(*MRI, Src->getReg()); in getDataRegClass()
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| H A D | SIRegisterInfo.cpp | 1041 const TargetRegisterClass *RC = getRegClassForReg(MF->getRegInfo(), ValueReg); in buildSpillLoadStore()
2237 SIRegisterInfo::getRegClassForReg(const MachineRegisterInfo &MRI, in getRegClassForReg() function in SIRegisterInfo
2244 const TargetRegisterClass *RC = getRegClassForReg(MRI, Reg); in isVGPR()
2251 const TargetRegisterClass *RC = getRegClassForReg(MRI, Reg); in isAGPR()
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| H A D | SIFixSGPRCopies.cpp | 841 TRI->getRegClassForReg(*MRI, SrcReg); in processPHINode()
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| H A D | SIFoldOperands.cpp | 694 const TargetRegisterClass *DestRC = TRI->getRegClassForReg(*MRI, DestReg); in foldOperand()
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| H A D | SIInstrInfo.cpp | 3806 const TargetRegisterClass *RC = RI.getRegClassForReg(MRI, Reg); in verifyInstruction()
3854 if (!MO.isReg() || !RI.hasVGPRs(RI.getRegClassForReg(MRI, MO.getReg()))) { in verifyInstruction()
5092 RI.getRegClassForReg(MRI, OpReg), OpSubReg); in legalizeGenericOperand()
6028 NewDstRC == RI.getRegClassForReg(MRI, Inst.getOperand(1).getReg())) { in moveToVALU()
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| H A D | SIISelLowering.cpp | 11368 auto *RC = TRI->getRegClassForReg(MRI, Op.getReg()); in AdjustInstrPostInstrSelection()
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