| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64RegisterBankInfo.cpp | 53 const RegisterBank &RBGPR = getRegBank(AArch64::GPRRegBankID); in AArch64RegisterBankInfo()
58 const RegisterBank &RBFPR = getRegBank(AArch64::FPRRegBankID); in AArch64RegisterBankInfo()
63 const RegisterBank &RBCCR = getRegBank(AArch64::CCRegBankID); in AArch64RegisterBankInfo()
253 return getRegBank(AArch64::FPRRegBankID); in getRegBankFromRegClass()
273 return getRegBank(AArch64::GPRRegBankID); in getRegBankFromRegClass()
275 return getRegBank(AArch64::CCRegBankID); in getRegBankFromRegClass()
504 auto *RB = getRegBank(MI.getOperand(0).getReg(), MRI, TRI); in hasFPConstraints()
622 const RegisterBank *DstRB = getRegBank(DstReg, MRI, TRI); in getInstrMapping()
623 const RegisterBank *SrcRB = getRegBank(SrcReg, MRI, TRI); in getInstrMapping()
693 (getRegBank(ScalarReg, MRI, TRI) == &AArch64::FPRRegBank || in getInstrMapping()
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| H A D | AArch64InstructionSelector.cpp | 645 const RegisterBank *OpBank = RBI.getRegBank(MO.getReg(), MRI, TRI); in unsupportedBinOp()
835 const RegisterBank &DstRegBank = *RBI.getRegBank(DstReg, MRI, TRI); in getRegClassesForCopy()
836 const RegisterBank &SrcRegBank = *RBI.getRegBank(SrcReg, MRI, TRI); in getRegClassesForCopy()
860 const RegisterBank &DstRegBank = *RBI.getRegBank(DstReg, MRI, TRI); in selectCopy()
861 const RegisterBank &SrcRegBank = *RBI.getRegBank(SrcReg, MRI, TRI); in selectCopy()
1046 assert(RBI.getRegBank(False, MRI, TRI)->getID() == in emitSelect()
1047 RBI.getRegBank(True, MRI, TRI)->getID() && in emitSelect()
1056 if (RBI.getRegBank(True, MRI, TRI)->getID() != AArch64::GPRRegBankID) { in emitSelect()
1443 assert(RBI.getRegBank(CompareReg, MRI, TRI)->getID() == in emitCBZ()
1732 getRegClassForTypeOnBank(Ty, RBI.getRegBank(AArch64::FPRRegBankID), RBI); in selectVectorAshrLshr()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARM/ |
| H A D | ARMInstructionSelector.cpp | 189 const RegisterBank *RegBank = RBI.getRegBank(Reg, MRI, TRI); in guessRegClass()
243 RBI.getRegBank(VReg0, MRI, TRI)->getID() == ARM::FPRRegBankID && in selectMergeValues()
248 RBI.getRegBank(VReg1, MRI, TRI)->getID() == ARM::GPRRegBankID && in selectMergeValues()
253 RBI.getRegBank(VReg2, MRI, TRI)->getID() == ARM::GPRRegBankID && in selectMergeValues()
275 RBI.getRegBank(VReg0, MRI, TRI)->getID() == ARM::GPRRegBankID && in selectUnmergeValues()
280 RBI.getRegBank(VReg1, MRI, TRI)->getID() == ARM::GPRRegBankID && in selectUnmergeValues()
285 RBI.getRegBank(VReg2, MRI, TRI)->getID() == ARM::FPRRegBankID && in selectUnmergeValues()
518 if (RBI.getRegBank(Reg, MRI, TRI)->getID() != ExpectedRegBankID) { in validReg()
919 const auto &SrcRegBank = *RBI.getRegBank(SrcReg, MRI, TRI); in select()
920 const auto &DstRegBank = *RBI.getRegBank(DstReg, MRI, TRI); in select()
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| H A D | ARMRegisterBankInfo.cpp | 142 const RegisterBank &RBGPR = getRegBank(ARM::GPRRegBankID); in ARMRegisterBankInfo()
200 return getRegBank(ARM::GPRRegBankID); in getRegBankFromRegClass()
207 return getRegBank(ARM::FPRRegBankID); in getRegBankFromRegClass()
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| /netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/GlobalISel/ |
| H A D | RegisterBankInfo.h | 432 RegisterBank &getRegBank(unsigned ID) { in getRegBank() function
576 const RegisterBank &getRegBank(unsigned ID) const { in getRegBank() function
577 return const_cast<RegisterBankInfo *>(this)->getRegBank(ID); in getRegBank()
585 const RegisterBank *getRegBank(Register Reg, const MachineRegisterInfo &MRI,
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUInstructionSelector.cpp | 283 const RegisterBank *DstRB = RBI.getRegBank(DstReg, *MRI, TRI); in selectG_AND_OR_XOR()
310 const RegisterBank *DstRB = RBI.getRegBank(DstReg, *MRI, TRI); in selectG_ADD_SUB()
482 const RegisterBank *SrcBank = RBI.getRegBank(SrcReg, *MRI, TRI); in selectG_EXTRACT()
514 const RegisterBank *DstBank = RBI.getRegBank(DstReg, *MRI, TRI); in selectG_MERGE_VALUES()
556 const RegisterBank *SrcBank = RBI.getRegBank(SrcReg, *MRI, TRI); in selectG_UNMERGE_VALUES()
599 const RegisterBank *DstBank = RBI.getRegBank(Dst, *MRI, TRI); in selectG_BUILD_VECTOR_TRUNC()
724 const RegisterBank *DstBank = RBI.getRegBank(DstReg, *MRI, TRI); in selectG_INSERT()
730 const RegisterBank *Src0Bank = RBI.getRegBank(Src0Reg, *MRI, TRI); in selectG_INSERT()
731 const RegisterBank *Src1Bank = RBI.getRegBank(Src1Reg, *MRI, TRI); in selectG_INSERT()
1132 const RegisterBank *DstBank = RBI.getRegBank(DstReg, *MRI, TRI); in selectRelocConstant()
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| H A D | AMDGPURegisterBankInfo.cpp | 124 const RegisterBank *SrcBank = RBI.getRegBank(SrcReg, MRI, *RBI.TRI); in applyBank()
150 const RegisterBank *DstBank = RBI.getRegBank(DstReg, MRI, *RBI.TRI); in applyBank()
205 assert(&getRegBank(AMDGPU::SGPRRegBankID) == &AMDGPU::SGPRRegBank && in AMDGPURegisterBankInfo()
206 &getRegBank(AMDGPU::VGPRRegBankID) == &AMDGPU::VGPRRegBank && in AMDGPURegisterBankInfo()
207 &getRegBank(AMDGPU::AGPRRegBankID) == &AMDGPU::AGPRRegBank); in AMDGPURegisterBankInfo()
654 const RegisterBank *Bank = getRegBank(Reg, *MRI, *TRI); in split64BitValueForMapping()
742 const RegisterBank *DefBank = getRegBank(Def.getReg(), MRI, *TRI); in executeInWaterfallLoop()
841 const RegisterBank *OpBank = getRegBank(OpReg, MRI, *TRI); in executeInWaterfallLoop()
1049 const RegisterBank *OpBank = getRegBank(Reg, MRI, *TRI); in collectWaterfallOperands()
1084 const RegisterBank *Bank = getRegBank(Reg, MRI, *TRI); in constrainOpWithReadfirstlane()
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| H A D | AMDGPURegBankCombiner.cpp | 69 return RBI.getRegBank(Reg, MRI, TRI)->getID() == AMDGPU::VGPRRegBankID; in isVgprRegBank()
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| /netbsd-src/external/apache2/llvm/dist/llvm/utils/TableGen/ |
| H A D | CodeGenTarget.h | 108 CodeGenRegBank &getRegBank() const;
127 return *getRegBank().getRegClass(R); in getRegisterClass()
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| H A D | DAGISelMatcherGen.cpp | 27 const CodeGenRegister *Reg = T.getRegBank().getReg(R); in getRegisterValueType()
29 for (const auto &RC : T.getRegBank().getRegClasses()) { in getRegisterValueType()
686 CGP.getTargetInfo().getRegBank().getReg(Def); in EmitResultLeafAsOperand()
732 const CodeGenRegBank &RB = CGP.getTargetInfo().getRegBank(); in EmitResultLeafAsOperand()
898 CGP.getTargetInfo().getRegBank().getReg(PhysRegInputs[i].first); in EmitResultInstructionAsOperand()
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| H A D | RegisterBankEmitter.cpp | 215 const CodeGenRegBank &RegisterClassHierarchy = Target.getRegBank(); in emitBaseClassImplementation()
280 const CodeGenRegBank &RegisterClassHierarchy = Target.getRegBank(); in run()
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| H A D | CodeGenTarget.cpp | 335 CodeGenRegBank &CodeGenTarget::getRegBank() const { in getRegBank() function in CodeGenTarget
398 return getRegBank().getRegistersByName().lookup(Name); in getRegisterByName()
403 const CodeGenRegister *Reg = getRegBank().getReg(R); in getRegisterVTs()
405 for (const auto &RC : getRegBank().getRegClasses()) { in getRegisterVTs()
420 for (const auto &RC : getRegBank().getRegClasses()) in ReadLegalValueTypes()
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| H A D | RegisterInfoEmitter.cpp | 62 CodeGenRegBank &RegBank = Target.getRegBank(); in RegisterInfoEmitter()
1063 BVE.add(Target.getRegBank().getReg(Reg)->EnumValue); in runMCDesc()
1646 CodeGenRegBank &RegBank = Target.getRegBank(); in run()
1664 CodeGenRegBank &RegBank = Target.getRegBank(); in debugDump()
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| H A D | FastISelEmitter.cpp | 270 RC = Target.getRegBank().getRegClassForRegister(OpLeafRec); in initialize()
439 PhysReg += Target.getRegBank().getReg(OpLeafRec)->getName(); in PhyRegForNode()
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| H A D | AsmMatcherEmitter.cpp | 1212 const auto &Registers = Target.getRegBank().getRegisters(); in buildRegisterClasses()
1213 auto &RegClassList = Target.getRegBank().getRegClasses(); in buildRegisterClasses()
2594 const auto &Regs = Target.getRegBank().getRegisters(); in emitMatchRegisterName()
2619 const auto &Regs = Target.getRegBank().getRegisters(); in emitMatchRegisterAltName()
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| H A D | CodeGenInstruction.cpp | 587 .contains(T.getRegBank().getReg(ADI->getDef()))) in tryAliasOpMatch()
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| H A D | AsmWriterEmitter.cpp | 606 const auto &Registers = Target.getRegBank().getRegisters(); in EmitGetRegisterName()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/X86/ |
| H A D | X86RegisterBankInfo.cpp | 32 const RegisterBank &RBGPR = getRegBank(X86::GPRRegBankID); in X86RegisterBankInfo()
53 return getRegBank(X86::GPRRegBankID); in getRegBankFromRegClass()
60 return getRegBank(X86::VECRRegBankID); in getRegBankFromRegClass()
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| H A D | X86InstructionSelector.cpp | 200 const RegisterBank &RegBank = *RBI.getRegBank(Reg, MRI, TRI); in getRegClass()
236 const RegisterBank &DstRegBank = *RBI.getRegBank(DstReg, MRI, TRI); in selectCopy()
240 const RegisterBank &SrcRegBank = *RBI.getRegBank(SrcReg, MRI, TRI); in selectCopy()
510 const RegisterBank &RB = *RBI.getRegBank(DefReg, MRI, TRI); in selectLoadStoreOp()
643 if (RBI.getRegBank(DefReg, MRI, TRI)->getID() != X86::GPRRegBankID) in selectConstant()
719 const RegisterBank &DstRB = *RBI.getRegBank(DstReg, MRI, TRI); in selectTruncOrPtrToInt()
720 const RegisterBank &SrcRB = *RBI.getRegBank(SrcReg, MRI, TRI); in selectTruncOrPtrToInt()
848 const RegisterBank &DstRB = *RBI.getRegBank(DstReg, MRI, TRI); in selectAnyext()
849 const RegisterBank &SrcRB = *RBI.getRegBank(SrcReg, MRI, TRI); in selectAnyext()
986 *getRegClass(LLT::scalar(8), *RBI.getRegBank(ResultReg, MRI, TRI)), MRI); in selectFCmp()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Mips/ |
| H A D | MipsRegisterBankInfo.cpp | 93 return getRegBank(Mips::GPRBRegBankID); in getRegBankFromRegClass()
102 return getRegBank(Mips::FPRBRegBankID); in getRegBankFromRegClass()
374 RBI.getRegBank(CopyInst->getOperand(Op).getReg(), MRI, TRI); in setTypesAccordingToPhysicalRegister()
704 MRI.setRegBank(Dest, getRegBank(Mips::GPRBRegBankID)); in setRegBank()
709 MRI.setRegBank(Dest, getRegBank(Mips::GPRBRegBankID)); in setRegBank()
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| H A D | MipsInstructionSelector.cpp | 97 return RBI.getRegBank(Reg, MRI, TRI)->getID() == Mips::GPRBRegBankID; in isRegInGprb()
102 return RBI.getRegBank(Reg, MRI, TRI)->getID() == Mips::FPRBRegBankID; in isRegInFprb()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/GlobalISel/ |
| H A D | RegisterBankInfo.cpp | 72 const RegisterBank &RegBank = getRegBank(Idx); in verify()
83 RegisterBankInfo::getRegBank(Register Reg, const MachineRegisterInfo &MRI, in getRegBank() function in RegisterBankInfo
196 const RegisterBank *AltRegBank = getRegBank(Reg, MRI, TRI); in getInstrMappingImpl()
241 const RegisterBank *AltRegBank = getRegBank(Reg, MRI, TRI); in getInstrMappingImpl()
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| H A D | RegBankSelect.cpp | 121 const RegisterBank *CurRegBank = RBI->getRegBank(Reg, *MRI, *TRI); in assignmentMatch()
244 const RegisterBank *CurRegBank = RBI->getRegBank(MO.getReg(), *MRI, *TRI); in getRepairCost()
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| /netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/MIRParser/ |
| H A D | MIParser.h | 147 const RegisterBank *getRegBank(StringRef Name);
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/MIRParser/ |
| H A D | MIParser.cpp | 298 const auto &RegBank = RBI->getRegBank(I); in initNames2RegBanks()
312 const RegisterBank *PerTargetMIParsingState::getRegBank(StringRef Name) { in getRegBank() function in PerTargetMIParsingState
1360 RegBank = PFS.Target.getRegBank(Name); in parseRegisterClassOrBank()
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