| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/X86/MCTargetDesc/ |
| H A D | X86BaseInfo.h | 1055 if (NumOps > 1 && Desc.getOperandConstraint(1, MCOI::TIED_TO) == 0) in getOperandBias()
1060 Desc.getOperandConstraint(6, MCOI::TIED_TO) == 0) in getOperandBias()
1065 if (NumOps >= 4 && Desc.getOperandConstraint(2, MCOI::TIED_TO) == 0 && in getOperandBias()
1066 Desc.getOperandConstraint(3, MCOI::TIED_TO) == 1) in getOperandBias()
1070 if (NumOps == 9 && Desc.getOperandConstraint(2, MCOI::TIED_TO) == 0 && in getOperandBias()
1071 (Desc.getOperandConstraint(3, MCOI::TIED_TO) == 1 || in getOperandBias()
1072 Desc.getOperandConstraint(8, MCOI::TIED_TO) == 1)) in getOperandBias()
|
| H A D | X86InstComments.cpp | 271 if (Desc.getOperandConstraint(MaskOp, MCOI::TIED_TO) != -1) in printMasking()
|
| /netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/MC/ |
| H A D | MCInstrDesc.h | 210 int getOperandConstraint(unsigned OpNum, in getOperandConstraint() function
|
| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/SystemZ/ |
| H A D | SystemZHazardRecognizer.cpp | 127 MID.getOperandConstraint(OpIdx, MCOI::TIED_TO) != -1) in has4RegOps()
|
| H A D | SystemZShortenInst.cpp | 68 if (MI.getDesc().getOperandConstraint(1, MCOI::TIED_TO) == 0 && in tieOpsIfNeeded()
|
| /netbsd-src/external/apache2/llvm/dist/llvm/tools/llvm-exegesis/lib/ |
| H A D | MCInstrDescView.cpp | 121 int TiedToIndex = Description->getOperandConstraint(OpIndex, MCOI::TIED_TO); in create()
|
| /netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | ScheduleDAGSDNodes.cpp | 214 if (MCID.getOperandConstraint(I, MCOI::TIED_TO) != -1) in ClusterNeighboringLoads()
454 if (MCID.getOperandConstraint(i, MCOI::TIED_TO) != -1) { in AddSchedEdges()
|
| H A D | ScheduleDAGFast.cpp | 256 if (MCID.getOperandConstraint(i, MCOI::TIED_TO) != -1) { in CopyAndMoveSuccessors()
|
| H A D | ScheduleDAGRRList.cpp | 1036 if (MCID.getOperandConstraint(i, MCOI::TIED_TO) != -1) { in TryUnfoldSU()
2826 if (MCID.getOperandConstraint(i+NumRes, MCOI::TIED_TO) != -1) { in canClobber()
3071 if (MCID.getOperandConstraint(j+NumRes, MCOI::TIED_TO) == -1) in AddPseudoTwoAddrDeps()
|
| H A D | InstrEmitter.cpp | 358 bool isTied = MCID.getOperandConstraint(Idx, MCOI::TIED_TO) != -1; in AddRegisterOperand()
|
| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/M68k/Disassembler/ |
| H A D | M68kDisassembler.cpp | 557 int TiedTo = Desc.getOperandConstraint(DstMIOpIdx, MCOI::TIED_TO); in getInstruction()
|
| /netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/ |
| H A D | TargetInstrInfo.cpp | 207 MI.getDesc().getOperandConstraint(Idx1, MCOI::TIED_TO) == 0) { in commuteInstructionImpl()
212 MI.getDesc().getOperandConstraint(Idx2, MCOI::TIED_TO) == 0) { in commuteInstructionImpl()
|
| H A D | MachineInstr.cpp | 289 int DefIdx = MCID->getOperandConstraint(OpNo, MCOI::TIED_TO); in addOperand()
294 if (MCID->getOperandConstraint(OpNo, MCOI::EARLY_CLOBBER) != -1) in addOperand()
1507 int ExpectedTiedIdx = MCID.getOperandConstraint(I, MCOI::TIED_TO); in hasComplexRegisterTies()
|
| H A D | MachineVerifier.cpp | 1821 int TiedTo = MCID.getOperandConstraint(MONum, MCOI::TIED_TO); in visitMachineOperand()
1865 if (-1 == MCID.getOperandConstraint(OtherIdx, MCOI::TIED_TO)) in visitMachineOperand()
|
| /netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/GlobalISel/ |
| H A D | Utils.cpp | 172 int DefIdx = I.getDesc().getOperandConstraint(OpI, MCOI::TIED_TO); in constrainSelectedInstRegOperands()
|
| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/Disassembler/ |
| H A D | AMDGPUDisassembler.cpp | 616 int Tied = MCII->get(MI.getOpcode()).getOperandConstraint(VDstIn_Idx, in getInstruction()
|
| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/AsmParser/ |
| H A D | AMDGPUAsmParser.cpp | 3329 Desc.getOperandConstraint(DstIdx, MCOI::EARLY_CLOBBER) == -1) { in validateEarlyClobberLimitations()
7437 && Desc.getOperandConstraint(OpNum + 1, MCOI::OperandConstraint::TIED_TO) == -1; in isRegOrImmWithInputMods()
7961 auto TiedTo = Desc.getOperandConstraint(Inst.getNumOperands(), in cvtDPP()
|
| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/X86/ |
| H A D | X86InstrInfo.cpp | 2642 if ((MI.getDesc().getOperandConstraint(Desc.getNumDefs(), in findCommutedOpIndices()
5526 NumOps > 1 && MI.getDesc().getOperandConstraint(1, MCOI::TIED_TO) != -1; in foldMemoryOperandImpl()
5636 0 == MI.getDesc().getOperandConstraint(CommuteOpIdx1, MCOI::TIED_TO); in foldMemoryOperandImpl()
5638 0 == MI.getDesc().getOperandConstraint(CommuteOpIdx2, MCOI::TIED_TO); in foldMemoryOperandImpl()
|
| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/ |
| H A D | PPCInstrInfo.cpp | 1181 assert(MI.getDesc().getOperandConstraint(0, MCOI::TIED_TO) && in commuteInstructionImpl()
|
| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/AsmParser/ |
| H A D | AArch64AsmParser.cpp | 4161 (MCID.getOperandConstraint(i, MCOI::TIED_TO) == -1) && in validateInstruction()
|
| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARM/Disassembler/ |
| H A D | ARMDisassembler.cpp | 859 int TiedOp = ARMInsts[MI.getOpcode()].getOperandConstraint( in AddThumbPredicate()
|
| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARM/AsmParser/ |
| H A D | ARMAsmParser.cpp | 2496 int TiedOp = MCID.getOperandConstraint(NextOpIndex, MCOI::TIED_TO); in addVPTPredROperands()
|
| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 11701 int DefIdx = MCID->getOperandConstraint(i, MCOI::TIED_TO); in AdjustInstrPostInstrSelection()
|