| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64PostLegalizerCombiner.cpp | 63 auto *FAddMI = getOpcodeDef(TargetOpcode::G_FADD, Src1, MRI); in matchExtractVecEltPairwiseAdd()
75 getOpcodeDef(TargetOpcode::G_SHUFFLE_VECTOR, Src1Op2, MRI); in matchExtractVecEltPairwiseAdd()
78 Shuffle = getOpcodeDef(TargetOpcode::G_SHUFFLE_VECTOR, Src1Op1, MRI); in matchExtractVecEltPairwiseAdd()
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| H A D | AArch64PostLegalizerLowering.cpp | 321 auto *InsMI = getOpcodeDef(TargetOpcode::G_INSERT_VECTOR_ELT, in matchDupFromInsertVectorElt()
326 if (!getOpcodeDef(TargetOpcode::G_IMPLICIT_DEF, InsMI->getOperand(1).getReg(), in matchDupFromInsertVectorElt()
346 auto *BuildVecMI = getOpcodeDef(TargetOpcode::G_BUILD_VECTOR, in matchDupFromBuildVector()
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| H A D | AArch64InstructionSelector.cpp | 1498 MachineInstr *AndInst = getOpcodeDef(TargetOpcode::G_AND, LHS, MRI); in tryOptCompareBranchFedByICmp()
1533 AndInst = getOpcodeDef(TargetOpcode::G_AND, LHS, MRI); in tryOptCompareBranchFedByICmp()
2142 MachineInstr *Cmp = getOpcodeDef(TargetOpcode::G_ICMP, CmpReg, MRI); in earlySelect()
2145 Cmp = getOpcodeDef(TargetOpcode::G_ICMP, CmpReg, MRI); in earlySelect()
2966 auto *LoadMI = getOpcodeDef(TargetOpcode::G_LOAD, SrcReg, MRI); in select()
4807 getOpcodeDef(TargetOpcode::G_CONSTANT, I.getOperand(Idx).getReg(), MRI); in tryOptConstantBuildVec()
4811 else if ((OpMI = getOpcodeDef(TargetOpcode::G_FCONSTANT, in tryOptConstantBuildVec()
5352 getOpcodeDef(TargetOpcode::G_PTR_ADD, Root.getReg(), MRI); in selectAddrModeShiftedExtendXReg()
5413 getOpcodeDef(TargetOpcode::G_PTR_ADD, Root.getReg(), MRI); in selectAddrModeXRO()
5486 getOpcodeDef(TargetOpcode::G_PTR_ADD, Root.getReg(), MRI); in selectAddrModeWRO()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/GlobalISel/ |
| H A D | CombinerHelper.cpp | 671 if (auto *LoadMI = getOpcodeDef(TargetOpcode::G_SEXTLOAD, LoadUser, MRI)) { in matchSextTruncSextLoad()
699 MachineInstr *LoadDef = getOpcodeDef(TargetOpcode::G_LOAD, SrcReg, MRI); in matchSextInRegOfLoad()
831 MachineInstr *AddrDef = getOpcodeDef(TargetOpcode::G_PTR_ADD, Addr, MRI); in findPreIndexCandidate()
1234 MachineInstr *FIDef = getOpcodeDef(TargetOpcode::G_FRAME_INDEX, Dst, MRI); in optimizeMemset()
1349 MachineInstr *FIDef = getOpcodeDef(TargetOpcode::G_FRAME_INDEX, Dst, MRI); in optimizeMemcpy()
1455 MachineInstr *FIDef = getOpcodeDef(TargetOpcode::G_FRAME_INDEX, Dst, MRI); in optimizeMemmove()
2571 getOpcodeDef(TargetOpcode::G_IMPLICIT_DEF, MO.getReg(), MRI); in matchAnyExplicitUseIsUndef()
2578 getOpcodeDef(TargetOpcode::G_IMPLICIT_DEF, MO.getReg(), MRI); in matchAllExplicitUsesAreUndef()
2590 return getOpcodeDef(TargetOpcode::G_IMPLICIT_DEF, MI.getOperand(0).getReg(), in matchUndefStore()
2596 return getOpcodeDef(TargetOpcode::G_IMPLICIT_DEF, MI.getOperand(1).getReg(), in matchUndefSelectCmp()
[all …]
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| H A D | Utils.cpp | 418 MachineInstr *llvm::getOpcodeDef(unsigned Opcode, Register Reg, in getOpcodeDef() function in llvm
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| H A D | LegalizerHelper.cpp | 4466 getOpcodeDef(TargetOpcode::G_CONSTANT, Amt, MRI)) { in narrowScalarShift()
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| /netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/GlobalISel/ |
| H A D | Utils.h | 201 MachineInstr *getOpcodeDef(unsigned Opcode, Register Reg,
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| H A D | LegalizationArtifactCombiner.h | 324 if (MachineInstr *DefMI = getOpcodeDef(TargetOpcode::G_IMPLICIT_DEF, in tryFoldImplicitDef()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPULegalizerInfo.cpp | 2585 if (MachineInstr *SrcFNeg = getOpcodeDef(AMDGPU::G_FNEG, ModSrc, MRI)) { in stripAnySourceMods()
2587 if (MachineInstr *SrcFAbs = getOpcodeDef(AMDGPU::G_FABS, ModSrc, MRI)) in stripAnySourceMods()
2589 } else if (MachineInstr *SrcFAbs = getOpcodeDef(AMDGPU::G_FABS, ModSrc, MRI)) in stripAnySourceMods()
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| H A D | AMDGPUInstructionSelector.cpp | 2192 MachineInstr *Fabs = getOpcodeDef(TargetOpcode::G_FABS, Src, *MRI); in selectG_FNEG()
4035 = getOpcodeDef(TargetOpcode::G_PTR_ADD, Data.N0, *MRI)) { in parseMUBUFAddress()
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| H A D | AMDGPURegisterBankInfo.cpp | 1380 MachineInstr *Add = getOpcodeDef(AMDGPU::G_ADD, CombinedOffset, *MRI); in setBufferOffsets()
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