Home
last modified time | relevance | path

Searched refs:getOpRegClass (Results 1 – 5 of 5) sorted by relevance

/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
H A DSIFixSGPRCopies.cpp664 if (TRI->hasVectorRegisters(TII->getOpRegClass(MI, 0)) || in runOnMachineFunction()
813 TII->getOpRegClass(*UseMI, UseMI->getOperandNo(&Use)); in processPHINode()
H A DSIInstrInfo.h863 const TargetRegisterClass *getOpRegClass(const MachineInstr &MI,
889 return RI.getRegSizeInBits(*getOpRegClass(MI, OpNo)) / 8; in getOpSize()
H A DSIInstrInfo.cpp292 EltSize = TRI->getRegSizeInBits(*getOpRegClass(LdSt, 0)) / 16; in getMemOperandsWithOffsetWidth()
296 EltSize = TRI->getRegSizeInBits(*getOpRegClass(LdSt, Data0Idx)) / 8; in getMemOperandsWithOffsetWidth()
1803 const TargetRegisterClass *EltRC = getOpRegClass(MI, 2); in expandPostRAPseudo()
3952 const TargetRegisterClass *DstRC = getOpRegClass(MI, DstIdx); in verifyInstruction()
4232 const TargetRegisterClass *RC = getOpRegClass(MI, VAddr0Idx); in verifyInstruction()
4484 const TargetRegisterClass *SIInstrInfo::getOpRegClass(const MachineInstr &MI, in getOpRegClass() function in SIInstrInfo
5412 if (VRC || !RI.isSGPRClass(getOpRegClass(MI, 0))) { in legalizeOperands()
5415 if (getOpRegClass(MI, 0) == &AMDGPU::VReg_1RegClass) { in legalizeOperands()
5418 VRC = RI.hasAGPRs(getOpRegClass(MI, 0)) in legalizeOperands()
5422 VRC = RI.hasAGPRs(getOpRegClass(MI, 0)) in legalizeOperands()
[all …]
H A DSIInsertWaitcnts.cpp487 const TargetRegisterClass *RC = TII->getOpRegClass(*MI, OpNo); in getRegInterval()
H A DSIISelLowering.cpp11300 uint32_t DstSize = TRI.getRegSizeInBits(*TII->getOpRegClass(MI, DstIdx)) / 32; in AddIMGInit()
11305 Register PrevDst = MRI.createVirtualRegister(TII->getOpRegClass(MI, DstIdx)); in AddIMGInit()
11316 NewDst = MRI.createVirtualRegister(TII->getOpRegClass(MI, DstIdx)); in AddIMGInit()