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Searched refs:getNumMicroOps (Results 1 – 14 of 14) sorted by relevance

/netbsd-src/external/apache2/llvm/dist/llvm/lib/MCA/Stages/
H A DDispatchStage.cpp63 const unsigned NumMicroOps = IR.getInstruction()->getNumMicroOps(); in checkRCU()
82 const unsigned NumMicroOps = IS.getNumMicroOps(); in dispatch()
161 unsigned NumMicroOps = Inst.getNumMicroOps(); in isAvailable()
H A DExecuteStage.cpp60 NumIssuedOpcodes += IS.getNumMicroOps(); in issueInstruction()
203 unsigned NumMicroOps = Inst.getNumMicroOps(); in execute()
H A DInOrderIssueStage.cpp40 unsigned NumMicroOps = Inst.getNumMicroOps(); in isAvailable()
240 unsigned NumMicroOps = IS.getNumMicroOps(); in tryIssue()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/
H A DTargetSchedule.cpp107 unsigned TargetSchedModel::getNumMicroOps(const MachineInstr *MI, in getNumMicroOps() function in TargetSchedModel
110 int UOps = InstrItins.getNumMicroOps(MI->getDesc().getSchedClass()); in getNumMicroOps()
111 return (UOps >= 0) ? UOps : TII->getNumMicroOps(&InstrItins, *MI); in getNumMicroOps()
H A DMachineScheduler.cpp2027 RemIssueCount += SchedModel->getNumMicroOps(SU.getInstr(), SC) in init()
2171 unsigned uops = SchedModel->getNumMicroOps(SU->getInstr()); in checkHazard()
2174 << SchedModel->getNumMicroOps(SU->getInstr()) << '\n'); in checkHazard()
2393 unsigned IncMOps = SchedModel->getNumMicroOps(SU->getInstr()); in bumpNode()
H A DTargetInstrInfo.cpp1120 unsigned TargetInstrInfo::getNumMicroOps(const InstrItineraryData *ItinData, in getNumMicroOps() function in TargetInstrInfo
/netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/
H A DTargetSchedule.h109 unsigned getNumMicroOps(const MachineInstr *MI,
H A DTargetInstrInfo.h1570 virtual unsigned getNumMicroOps(const InstrItineraryData *ItinData,
/netbsd-src/external/apache2/llvm/dist/llvm/lib/MCA/HardwareUnits/
H A DRetireControlUnit.cpp45 unsigned Entries = normalizeQuantity(Inst.getNumMicroOps()); in dispatch()
/netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/MC/
H A DMCInstrItineraries.h228 int getNumMicroOps(unsigned ItinClassIndx) const { in getNumMicroOps() function
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/
H A DHexagonMachineScheduler.cpp340 unsigned uops = SchedModel->getNumMicroOps(SU->getInstr()); in checkHazard()
407 IssueCount += SchedModel->getNumMicroOps(SU->getInstr()); in bumpNode()
/netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/MCA/
H A DInstruction.h422 unsigned getNumMicroOps() const { return Desc.NumMicroOps; } in getNumMicroOps() function
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
H A DARMBaseInstrInfo.h316 unsigned getNumMicroOps(const InstrItineraryData *ItinData,
H A DARMBaseInstrInfo.cpp3430 int UOps = ItinData->getNumMicroOps(Desc.getSchedClass()); in getNumMicroOpsSwiftLdSt()
3727 unsigned ARMBaseInstrInfo::getNumMicroOps(const InstrItineraryData *ItinData, in getNumMicroOps() function in ARMBaseInstrInfo
3734 int ItinUOps = ItinData->getNumMicroOps(Class); in getNumMicroOps()
4739 if (!ItinData->isEmpty() && ItinData->getNumMicroOps(Class) < 0) in getInstrLatency()
4740 return getNumMicroOps(ItinData, MI); in getInstrLatency()