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Searched refs:getNumDefs (Results 1 – 25 of 56) sorted by relevance

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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/MCTargetDesc/
H A DHexagonMCChecker.cpp95 for (unsigned i = MCID.getNumDefs(); i < MCID.getNumOperands(); ++i) in init()
131 for (unsigned i = 0; i < MCID.getNumDefs(); ++i) { in init()
188 for (unsigned i = MCID.getNumDefs(); i < MCID.getNumOperands(); ++i) in init()
506 unsigned Defs = HexagonMCInstrInfo::getDesc(MCII, Inst).getNumDefs(); in checkRegistersReadOnly()
523 for (unsigned j = HexagonMCInstrInfo::getDesc(MCII, I).getNumDefs(), in registerUsed()
541 for (unsigned J = 0, N = Desc.getNumDefs(); J < N; ++J) in registerProducer()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/
H A DFastISel.cpp1930 Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs()); in fastEmitInst_r()
1932 if (II.getNumDefs() >= 1) in fastEmitInst_r()
1951 Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs()); in fastEmitInst_rr()
1952 Op1 = constrainOperandRegClass(II, Op1, II.getNumDefs() + 1); in fastEmitInst_rr()
1954 if (II.getNumDefs() >= 1) in fastEmitInst_rr()
1974 Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs()); in fastEmitInst_rrr()
1975 Op1 = constrainOperandRegClass(II, Op1, II.getNumDefs() + 1); in fastEmitInst_rrr()
1976 Op2 = constrainOperandRegClass(II, Op2, II.getNumDefs() + 2); in fastEmitInst_rrr()
1978 if (II.getNumDefs() >= 1) in fastEmitInst_rrr()
2000 Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs()); in fastEmitInst_ri()
[all …]
H A DScheduleDAGSDNodes.cpp128 if (ResNo >= II.getNumDefs() && II.hasImplicitDefOfPhysReg(Reg)) in CheckForPhysRegDependency()
471 if (NumUsed > TII->get(N->getMachineOpcode()).getNumDefs()) in AddSchedEdges()
571 unsigned NRegDefs = SchedDAG->TII->get(Node->getMachineOpcode()).getNumDefs(); in InitNodeNumDefs()
658 OpIdx += TII->get(Use->getMachineOpcode()).getNumDefs(); in computeOperandLatency()
H A DScheduleDAGRRList.cpp1285 NumRes = MCID.getNumDefs(); in getPhysicalRegisterVT()
1418 for (unsigned i = 0; i < MCID.getNumDefs(); ++i) in DelayForLiveRegsBottomUp()
2117 unsigned NumDefs = TII->get(N->getMachineOpcode()).getNumDefs(); in MayReduceRegPressure()
2163 unsigned NumDefs = TII->get(N->getMachineOpcode()).getNumDefs(); in RegPressureDiff()
2292 unsigned NumDefs = TII->get(PN->getMachineOpcode()).getNumDefs(); in unscheduledNode()
2309 unsigned NumDefs = TII->get(N->getMachineOpcode()).getNumDefs(); in unscheduledNode()
2823 unsigned NumRes = MCID.getNumDefs(); in canClobber()
2880 unsigned NumDefs = TII->get(N->getMachineOpcode()).getNumDefs(); in canClobberPhysRegDefs()
3068 unsigned NumRes = MCID.getNumDefs(); in AddPseudoTwoAddrDeps()
H A DInstrEmitter.cpp137 if (i+II.getNumDefs() < II.getNumOperands()) { in EmitCopyFromReg()
139 TII->getRegClass(II, i+II.getNumDefs(), TRI, *MF)); in EmitCopyFromReg()
203 unsigned NumVRegs = HasVRegVariadicDefs ? NumResults : II.getNumDefs(); in CreateVirtualRegisters()
904 unsigned NumDefs = II.getNumDefs(); in EmitMachineNode()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/
H A DExecutionDomainFix.cpp239 e = MI->isVariadic() ? MI->getNumOperands() : MCID.getNumDefs(); in processDefs()
259 for (unsigned i = mi->getDesc().getNumDefs(), in visitHardInstr()
271 for (unsigned i = 0, e = mi->getDesc().getNumDefs(); i != e; ++i) { in visitHardInstr()
290 for (unsigned i = mi->getDesc().getNumDefs(), in visitSoftInstr()
H A DBreakFalseDeps.cpp193 for (unsigned i = MCID.getNumDefs(), e = MCID.getNumOperands(); i != e; ++i) { in processDefs()
215 e = MI->isVariadic() ? MI->getNumOperands() : MCID.getNumDefs(); in processDefs()
H A DPeepholeOptimizer.cpp875 NumDefs = MI.getDesc().getNumDefs(); in UncoalescableRewriter()
1175 assert(MI.getDesc().getNumDefs() == 1 && in optimizeCoalescableCopy()
1322 if (MCID.getNumDefs() != 1) in isLoadFoldable()
1343 if (MCID.getNumDefs() != 1) in isMoveImmediate()
1516 if (MI.getDesc().getNumDefs() != 1) in findTargetRecurrence()
1756 for (unsigned i = MIDesc.getNumDefs(); i != MI->getNumOperands(); in runOnMachineFunction()
1837 if (Def->getDesc().getNumDefs() != 1) in getNextSourceFromBitcast()
2053 (DefIdx < Def->getDesc().getNumDefs() || in getNextSourceImpl()
H A DDetectDeadLanes.cpp278 if (MI.getDesc().getNumDefs() != 1) in transferDefinedLanesStep()
426 assert(UseMI.getDesc().getNumDefs() == 1); in determineInitialUsedLanes()
H A DImplicitNullChecks.cpp371 if (MI.getDesc().getNumDefs() > 1) in isSuitableMemoryOp()
715 unsigned NumDefs = MI->getDesc().getNumDefs(); in insertFaultingInstr()
H A DMachineCSE.cpp610 unsigned NumDefs = MI->getNumDefs(); in ProcessBlockCSE()
792 MI->getNumDefs() != 1 || in isPRECandidate()
H A DTargetInstrInfo.cpp171 bool HasDef = MCID.getNumDefs(); in commuteInstructionImpl()
308 unsigned CommutableOpIdx1 = MCID.getNumDefs(); in findCommutedOpIndices()
489 return std::make_pair(MI.getNumDefs(), StatepointOpers(&MI).getVarIdx()); in getPatchpointUnfoldableRange()
H A DLiveRangeEdit.cpp294 MI->getDesc().getNumDefs() == 1) { in eliminateDeadDef()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/MCA/
H A DInstrBuilder.cpp224 unsigned NumExplicitDefs = MCDesc.getNumDefs(); in verifyOperands()
299 unsigned NumExplicitDefs = MCDesc.getNumDefs(); in populateWrites()
430 unsigned NumExplicitUses = MCDesc.getNumOperands() - MCDesc.getNumDefs(); in populateReads()
439 for (unsigned I = 0, OpIndex = MCDesc.getNumDefs(); I < NumExplicitUses; in populateReads()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/WebAssembly/MCTargetDesc/
H A DWebAssemblyInstPrinter.cpp300 else if (OpNo >= Desc.getNumDefs() && !IsVariadicDef) in printOperand()
307 if (OpNo < MII.get(MI->getOpcode()).getNumDefs() || IsVariadicDef) in printOperand()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
H A DAArch64DeadRegisterDefinitionsPass.cpp142 for (int I = 0, E = Desc.getNumDefs(); I != E; ++I) { in processMachineBasicBlock()
H A DAArch64FastISel.cpp1118 constrainOperandRegClass(II, Addr.getReg(), II.getNumDefs()+Idx)); in addLoadStoreOperands()
1120 constrainOperandRegClass(II, Addr.getOffsetReg(), II.getNumDefs()+Idx+1)); in addLoadStoreOperands()
1309 LHSReg = constrainOperandRegClass(II, LHSReg, II.getNumDefs()); in emitAddSub_rr()
1310 RHSReg = constrainOperandRegClass(II, RHSReg, II.getNumDefs() + 1); in emitAddSub_rr()
1354 LHSReg = constrainOperandRegClass(II, LHSReg, II.getNumDefs()); in emitAddSub_ri()
1395 LHSReg = constrainOperandRegClass(II, LHSReg, II.getNumDefs()); in emitAddSub_rs()
1396 RHSReg = constrainOperandRegClass(II, RHSReg, II.getNumDefs() + 1); in emitAddSub_rs()
1439 LHSReg = constrainOperandRegClass(II, LHSReg, II.getNumDefs()); in emitAddSub_rx()
1440 RHSReg = constrainOperandRegClass(II, RHSReg, II.getNumDefs() + 1); in emitAddSub_rx()
2118 SrcReg = constrainOperandRegClass(II, SrcReg, II.getNumDefs()); in emitStore()
[all …]
/netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/GlobalISel/
H A DLocalizer.cpp89 assert(MI.getDesc().getNumDefs() == 1 && in localizeInterBlock()
H A DCombinerHelper.cpp2080 for (unsigned Idx = 1, EndIdx = MI.getNumDefs(); Idx != EndIdx; ++Idx) { in matchCombineUnmergeWithDeadLanesToTrunc()
2089 Register SrcReg = MI.getOperand(MI.getNumDefs()).getReg(); in applyCombineUnmergeWithDeadLanesToTrunc()
2119 Register SrcReg = MI.getOperand(MI.getNumDefs()).getReg(); in matchCombineUnmergeZExtToZExt()
2142 MRI.getVRegDef(MI.getOperand(MI.getNumDefs()).getReg()); in applyCombineUnmergeZExtToZExt()
2161 for (unsigned Idx = 1, EndIdx = MI.getNumDefs(); Idx != EndIdx; ++Idx) { in applyCombineUnmergeZExtToZExt()
2749 assert(MI.getNumDefs() == 1 && "Expected only one def?"); in replaceInstWithFConstant()
2757 assert(MI.getNumDefs() == 1 && "Expected only one def?"); in replaceInstWithConstant()
2765 assert(MI.getNumDefs() == 1 && "Expected only one def?"); in replaceInstWithUndef()
/netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/MC/
H A DMCInstrDesc.h243 unsigned getNumDefs() const { return NumDefs; } in getNumDefs() function
/netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/
H A DStackMaps.h174 NumDefs = MI->getNumDefs(); in StatepointOpers()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/SystemZ/
H A DSystemZHazardRecognizer.cpp126 if (OpIdx >= MID.getNumDefs() && in has4RegOps()
/netbsd-src/external/apache2/llvm/dist/llvm/tools/llvm-exegesis/lib/
H A DAssembler.cpp102 const bool IsDef = OpIndex < MCID.getNumDefs(); in addInstruction()
H A DMCInstrDescView.cpp117 Operand.IsDef = (OpIndex < Description->getNumDefs()); in create()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/WebAssembly/
H A DWebAssemblyMCInstLower.cpp239 unsigned NumVariadicDefs = MI->getNumExplicitDefs() - Desc.getNumDefs(); in lower()

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