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Searched refs:getInstr (Results 1 – 25 of 87) sorted by relevance

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/netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/AsmPrinter/
H A DDebugHandlerBase.cpp299 Entries.front().getInstr()->getDebugVariable(); in beginFunction()
302 Entries.front().getInstr()->getParent()->sameSection(&MF->front())) { in beginFunction()
303 if (!IsDescribedByReg(Entries.front().getInstr())) in beginFunction()
304 LabelsBeforeInsn[Entries.front().getInstr()] = Asm->getFunctionBegin(); in beginFunction()
305 if (Entries.front().getInstr()->getDebugExpression()->isFragment()) { in beginFunction()
310 const DIExpression *Fragment = I->getInstr()->getDebugExpression(); in beginFunction()
315 Pred.getInstr()->getDebugExpression()); in beginFunction()
322 if (IsDescribedByReg(I->getInstr())) in beginFunction()
324 LabelsBeforeInsn[I->getInstr()] = Asm->getFunctionBegin(); in beginFunction()
331 requestLabelBeforeInsn(Entry.getInstr()); in beginFunction()
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H A DDbgEntityHistoryCalculator.cpp80 Entries.back().getInstr()->isIdenticalTo(MI)) { in startDbgValue()
82 << "\t" << Entries.back().getInstr() << "\t" << MI in startDbgValue()
96 if (Entries.back().isClobber() && Entries.back().getInstr() == &MI) in startClobber()
198 const MachineInstr *StartMI = EI->getInstr(); in trimLocationRanges()
200 ? HistoryMapEntries[EndIndex].getInstr() in trimLocationRanges()
265 const MachineInstr *MI = Entry.getInstr(); in hasNonEmptyLocation()
339 if (Entry.getInstr()->isDebugEntryValue()) in clobberRegEntries()
341 if (Entry.getInstr()->hasDebugOperandForReg(RegNo)) { in clobberRegEntries()
344 for (auto &MO : Entry.getInstr()->debug_operands()) in clobberRegEntries()
348 for (auto &MO : Entry.getInstr()->debug_operands()) in clobberRegEntries()
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/
H A DHexagonSubtarget.cpp216 MachineInstr &MI1 = *SU.getInstr(); in apply()
225 MachineInstr &MI2 = *SI.getSUnit()->getInstr(); in apply()
253 if (Inst1.getInstr()->getOpcode() != Hexagon::A2_tfrpi) in shouldTFRICallBind()
257 unsigned Type = HII.getType(*Inst2.getInstr()); in shouldTFRICallBind()
277 if (DAG->SUnits[su].getInstr()->isCall()) in apply()
280 else if (DAG->SUnits[su].getInstr()->isCompare() && LastSequentialCall) in apply()
301 const MachineInstr *MI = DAG->SUnits[su].getInstr(); in apply()
343 MachineInstr &L0 = *S0.getInstr(); in apply()
356 MachineInstr &L1 = *S1.getInstr(); in apply()
395 MachineInstr *SrcInst = Src->getInstr(); in adjustSchedDependency()
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H A DHexagonMachineScheduler.cpp74 if (QII.mayBeCurLoad(*SUd->getInstr())) in hasDependence()
77 if (QII.canExecuteInBundle(*SUd->getInstr(), *SUu->getInstr())) in hasDependence()
98 if (!SU || !SU->getInstr()) in isResourceAvailable()
103 switch (SU->getInstr()->getOpcode()) { in isResourceAvailable()
105 if (!ResourcesModel->canReserveResources(*SU->getInstr())) in isResourceAvailable()
119 MachineBasicBlock *MBB = SU->getInstr()->getParent(); in isResourceAvailable()
157 switch (SU->getInstr()->getOpcode()) { in reserveResources()
159 ResourcesModel->reserveResources(*SU->getInstr()); in reserveResources()
181 LLVM_DEBUG(Packet[i]->getInstr()->dump()); in reserveResources()
308 assert(SU->getInstr() && "Scheduled SUnit must have instr"); in releaseBottomNode()
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H A DHexagonHazardRecognizer.cpp40 MachineInstr *MI = SU->getInstr(); in getHazardType()
103 if (UsesLoad && SU->isInstr() && SU->getInstr()->mayLoad()) in ShouldPreferAnother()
109 MachineInstr *MI = SU->getInstr(); in EmitInstruction()
160 TII->mayBeNewStore(*S.getSUnit()->getInstr()) && in EmitInstruction()
161 Resources->canReserveResources(*S.getSUnit()->getInstr())) { in EmitInstruction()
H A DHexagonVLIWPacketizer.cpp424 if (PacketSU->getInstr()->isInlineAsm()) in canPromoteToDotCur()
518 assert(SUI->getInstr() && SUJ->getInstr()); in updateOffset()
519 MachineInstr &MI = *SUI->getInstr(); in updateOffset()
520 MachineInstr &MJ = *SUJ->getInstr(); in updateOffset()
675 if (PacketSU->getInstr()->mayStore()) in canPromoteToNewValueStore()
761 MachineInstr &TempMI = *TempSU->getInstr(); in canPromoteToNewValueStore()
774 if (MO.isReg() && TempSU->getInstr()->modifiesRegister(MO.getReg(), HRI)) in canPromoteToNewValueStore()
828 MachineInstr &PacketMI = *PacketSU->getInstr(); in canPromoteToNewValue()
861 const MachineInstr &PI = *PacketSU->getInstr(); in canPromoteToDotNew()
1319 assert(SUI->getInstr() && SUJ->getInstr()); in isLegalToPacketizeTogether()
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H A DHexagonISelLoweringHVX.cpp622 SDValue HalfV0 = getInstr(Hexagon::V6_vd0, dl, VecTy, {}, DAG); in buildHvxVectorReg()
623 SDValue HalfV1 = getInstr(Hexagon::V6_vd0, dl, VecTy, {}, DAG); in buildHvxVectorReg()
675 SDValue Q = getInstr(Hexagon::V6_pred_scalar2, dl, BoolTy, in createHvxPrefixPred()
845 return getInstr(Hexagon::C2_cmpgtui, dl, MVT::i1, {ExtB, Zero}, DAG); in extractHvxElementPred()
1014 return getInstr(Hexagon::A4_vcmpbgtui, dl, ResTy, in extractHvxSubvectorPred()
1139 SDValue Q = getInstr(Hexagon::V6_pred_scalar2, dl, BoolTy, in insertHvxSubvectorPred()
1141 ByteVec = getInstr(Hexagon::V6_vmux, dl, ByteTy, {Q, ByteSub, ByteVec}, DAG); in insertHvxSubvectorPred()
1208 SDValue Vrmpy = getInstr(Hexagon::V6_vrmpyub, dl, ByteTy, {Sel, All1}, DAG); in compressHvxPred()
1210 SDValue Rot = getInstr(Hexagon::V6_valignbi, dl, ByteTy, in compressHvxPred()
1499 SDValue M = getInstr(MpyOpc, dl, ExtTy, {Vs, Vt}, DAG); in LowerHvxMulh()
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/netbsd-src/external/apache2/llvm/dist/llvm/tools/llvm-exegesis/lib/
H A DSnippetGenerator.cpp48 if (Variant.getInstr().hasMemoryOperands()) { in generateConfigurations()
59 for (const auto &Op : Variant.getInstr().Operands) { in generateConfigurations()
121 for (const Operand &Op : IT.getInstr().Operands) { in computeRegisterInitialValues()
131 for (const Operand &Op : IT.getInstr().Operands) { in computeRegisterInitialValues()
144 const AliasingConfigurations SelfAliasing(Variant.getInstr(), in generateSelfAliasingCodeTemplates()
145 Variant.getInstr()); in generateSelfAliasingCodeTemplates()
264 for (const Variable &Var : IT.getInstr().Variables) { in randomizeUnsetVariables()
267 if (auto Err = randomizeMCOperand(State, IT.getInstr(), Var, in randomizeUnsetVariables()
H A DSerialSnippetGenerator.cpp51 const Instruction &OtherInstr = State.getIC().getInstr(OtherOpcode); in computeAliasingInstructions()
118 const AliasingConfigurations SelfAliasing(Variant.getInstr(), in appendCodeTemplates()
119 Variant.getInstr()); in appendCodeTemplates()
133 const Instruction &Instr = Variant.getInstr(); in appendCodeTemplates()
166 getExecutionModes(Variant.getInstr(), ForbiddenRegisters); in generateCodeTemplates()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
H A DR600MachineScheduler.cpp156 for (MachineInstr::mop_iterator It = SU->getInstr()->operands_begin(), in schedNode()
157 E = SU->getInstr()->operands_end(); It != E; ++It) { in schedNode()
190 if (isPhysicalRegCopy(SU->getInstr())) { in releaseBottomNode()
215 MachineInstr *MI = SU->getInstr(); in getAluKind()
289 int Opcode = SU->getInstr()->getOpcode(); in getInstKind()
318 InstructionsGroupCandidate.push_back(SU->getInstr()); in PopInst()
320 (!AnyALU || !TII->isVectorOnly(*SU->getInstr()))) { in PopInst()
389 AssignSlot(UnslotedSU->getInstr(), Slot); in AttemptFillSlot()
438 InstructionsGroupCandidate.push_back(SU->getInstr()); in pickAlu()
H A DGCNDPPCombine.cpp240 if (!TII->isOperandLegal(*DPPInst.getInstr(), NumOperands, Src0)) { in createDPPInst()
262 if (!TII->isOperandLegal(*DPPInst.getInstr(), NumOperands, Src1)) { in createDPPInst()
272 if (!TII->getNamedOperand(*DPPInst.getInstr(), AMDGPU::OpName::src2) || in createDPPInst()
273 !TII->isOperandLegal(*DPPInst.getInstr(), NumOperands, Src2)) { in createDPPInst()
288 DPPInst.getInstr()->eraseFromParent(); in createDPPInst()
291 LLVM_DEBUG(dbgs() << " combined: " << *DPPInst.getInstr()); in createDPPInst()
292 return DPPInst.getInstr(); in createDPPInst()
486 DPPMIs.push_back(UndefInst.getInstr()); in combineDPPMov()
H A DSIMachineScheduler.cpp252 TopRPTracker.getDownwardPressure(SU->getInstr(), pressure, MaxPressure); in pickNode()
319 RPTracker.setPos(SU->getInstr()); in initRegPressure()
400 TopRPTracker.setPos(SU->getInstr()); in schedule()
1127 if (SIInstrInfo::isEXP(*SU.getInstr())) { in colorExports()
1151 if (!SIInstrInfo::isEXP(*DAG->SUnits[k].getInstr())) in colorExports()
1336 MachineInstr *MI = SU->getInstr(); in scheduleInsideBlocks()
1365 Block->schedule((*SUs.begin())->getInstr(), (*SUs.rbegin())->getInstr()); in scheduleInsideBlocks()
1813 if (SITII->isLowLatencyInstruction(*Pred->getInstr())) { in moveLowLatencies()
1823 if (SITII->isLowLatencyInstruction(*SU->getInstr())) { in moveLowLatencies()
1844 } else if (SU->getInstr()->getOpcode() == AMDGPU::COPY) { in moveLowLatencies()
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H A DAMDGPUExportClustering.cpp30 return SIInstrInfo::isEXP(*SU.getInstr()); in isExport()
34 const MachineInstr *MI = SU->getInstr(); in isPositionExport()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/
H A DScheduleDAGInstrs.cpp234 const MachineOperand &MO = SU->getInstr()->getOperand(OperIdx); in addPhysRegDataDeps()
242 const MCInstrDesc *DefMIDesc = &SU->getInstr()->getDesc(); in addPhysRegDataDeps()
264 RegUse = UseSU->getInstr(); in addPhysRegDataDeps()
267 (RegUse ? &UseSU->getInstr()->getDesc() : nullptr); in addPhysRegDataDeps()
272 Dep.setLatency(SchedModel.computeOperandLatency(SU->getInstr(), OperIdx, in addPhysRegDataDeps()
279 if (SU->getInstr()->isBundle() || (RegUse && RegUse->isBundle())) in addPhysRegDataDeps()
292 MachineInstr *MI = SU->getInstr(); in addPhysRegDeps()
317 !DefSU->getInstr()->registerDefIsDead(*Alias))) { in addPhysRegDeps()
321 SchedModel.computeOutputLatency(MI, OperIdx, DefSU->getInstr())); in addPhysRegDeps()
396 MachineInstr *MI = SU->getInstr(); in addVRegDefDeps()
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H A DMachinePipeliner.cpp617 OrderedInsts.push_back(SU->getInstr()); in schedule()
618 Cycles[SU->getInstr()] = Cycle; in schedule()
619 Stages[SU->getInstr()] = Schedule.stageScheduled(SU); in schedule()
745 MachineInstr &MI = *SU.getInstr(); in addLoopCarriedDependences()
770 MachineInstr &LdMI = *Load->getInstr(); in addLoopCarriedDependences()
846 MachineInstr *MI = I.getInstr(); in updatePhiDependences()
902 MachineInstr *PMI = PI.getSUnit()->getInstr(); in updatePhiDependences()
904 if (I.getInstr()->isPHI()) { in updatePhiDependences()
927 if (!canUseLastOffsetValue(I.getInstr(), BasePos, OffsetPos, NewBase, in changeDependences()
932 Register OrigBase = I.getInstr()->getOperand(BasePos).getReg(); in changeDependences()
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H A DMacroFusion.cpp94 dbgs() << DAG.TII->getName(FirstSU.getInstr()->getOpcode()) << " - " in fuseInstructionPair()
95 << DAG.TII->getName(SecondSU.getInstr()->getOpcode()) << '\n';); in fuseInstructionPair()
161 if (DAG->ExitSU.getInstr()) in apply()
169 const MachineInstr &AnchorMI = *AnchorSU.getInstr(); in scheduleAdjacentImpl()
188 const MachineInstr *DepMI = DepSU.getInstr(); in scheduleAdjacentImpl()
H A DSlotIndexes.cpp125 assert(MIEntry.getInstr() == &MI && "Instruction indexes broken."); in removeMachineInstrFromMaps()
138 assert(MIEntry.getInstr() == &MI && "Instruction indexes broken."); in removeSingleMachineInstrFromMaps()
217 MachineInstr *SlotMI = ListI->getInstr(); in repairIndexesInRange()
254 if (ILE.getInstr()) { in dump()
255 dbgs() << *ILE.getInstr(); in dump()
H A DMachineScheduler.cpp799 MachineInstr *MI = SU->getInstr(); in schedule()
949 const MachineInstr &MI = *SU.getInstr(); in collectVRegUses()
1140 << PrintLaneMask(P.LaneMask) << ' ' << *SU.getInstr(); in updatePressureDiffs()
1169 LI.Query(LIS->getInstructionIndex(*SU->getInstr())); in updatePressureDiffs()
1174 << *SU->getInstr(); in updatePressureDiffs()
1185 if (EntrySU.getInstr() != nullptr) in dump()
1194 if (SchedModel.mustBeginGroup(SU.getInstr()) && in dump()
1195 SchedModel.mustEndGroup(SU.getInstr())) in dump()
1201 if (ExitSU.getInstr() != nullptr) in dump()
1366 LiveQueryResult LRQ = LI.Query(LIS->getInstructionIndex(*SU->getInstr())); in computeCyclicCriticalPath()
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/SystemZ/
H A DSystemZHazardRecognizer.cpp105 if (CurrGroupSize == 2 && has4RegOps(SU->getInstr())) in fitsIntoCurrentGroup()
169 OS << TII->getName(SU->getInstr()->getOpcode()); in dumpSU()
204 if (has4RegOps(SU->getInstr())) in dumpSU()
285 LastEmittedMI = SU->getInstr(); in EmitInstruction()
291 LastEmittedMI = SU->getInstr(); in EmitInstruction()
329 CurrGroupHas4RegOps |= has4RegOps(SU->getInstr()); in EmitInstruction()
364 if (CurrGroupSize == 2 && has4RegOps(SU->getInstr())) in groupingCost()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/
H A DPPCMachineScheduler.cpp25 return Cand.SU->getInstr()->getOpcode() == PPC::ADDI || in isADDIInstr()
26 Cand.SU->getInstr()->getOpcode() == PPC::ADDI8; in isADDIInstr()
37 if (isADDIInstr(FirstCand) && SecondCand.SU->getInstr()->mayLoad()) { in biasAddiLoadCandidate()
41 if (FirstCand.SU->getInstr()->mayLoad() && isADDIInstr(SecondCand)) { in biasAddiLoadCandidate()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/M68k/
H A DM68kInstrInfo.cpp373 LLVM_DEBUG(dbgs() << "Remove " << *MIB.getInstr() << '\n'); in ExpandMOVX_RR()
376 LLVM_DEBUG(dbgs() << "Expand " << *MIB.getInstr() << " to MOV\n"); in ExpandMOVX_RR()
388 LLVM_DEBUG(dbgs() << "Expand " << *MIB.getInstr() << " to "); in ExpandMOVSZX_RR()
419 BuildMI(MBB, MIB.getInstr(), DL, get(Move), Dst).addReg(SSrc); in ExpandMOVSZX_RR()
424 AddSExt(MBB, MIB.getInstr(), DL, Dst, MVTSrc, MVTDst); in ExpandMOVSZX_RR()
427 AddZExt(MBB, MIB.getInstr(), DL, Dst, MVTSrc, MVTDst); in ExpandMOVSZX_RR()
438 LLVM_DEBUG(dbgs() << "Expand " << *MIB.getInstr() << " to LOAD and "); in ExpandMOVSZX_RM()
456 MachineBasicBlock::iterator I = MIB.getInstr(); in ExpandMOVSZX_RM()
474 MachineBasicBlock::iterator I = MIB.getInstr(); in ExpandPUSH_POP()
510 auto MI = MIB.getInstr(); in ExpandMOVEM()
/netbsd-src/external/apache2/llvm/dist/llvm/tools/llvm-exegesis/lib/PowerPC/
H A DTarget.cpp19 const auto Op = IT.getInstr().Operands[OpIdx]; in setMemOp()
77 if (IT.getInstr().hasTiedRegisters()) in fillMemoryOperands()
80 const auto DispOp = IT.getInstr().Operands[DispOpIdx]; in fillMemoryOperands()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
H A DARMHazardRecognizer.cpp45 MachineInstr *MI = SU->getInstr(); in getHazardType()
88 MachineInstr *MI = SU->getInstr(); in EmitInstruction()
183 MachineInstr &L0 = *SU->getInstr(); in getHazardType()
255 MachineInstr &MI = *SU->getInstr(); in EmitInstruction()
H A DMVETPAndVPTOptimisationsPass.cpp251 LLVM_DEBUG(dbgs() << "Lowered WhileLoopStart into: " << *MI.getInstr()); in LowerWhileLoopStart()
406 LLVM_DEBUG(dbgs() << "Merged LoopDec and End into: " << *MI.getInstr()); in MergeLoopEnd()
501 << *MI.getInstr()); in ConvertTailPredLoop()
607 MIBuilder.getInstr()->dump()); in ReplaceRegisterUseWithVPNOT()
609 return *MIBuilder.getInstr(); in ReplaceRegisterUseWithVPNOT()
856 MIBuilder.getInstr()->dump(); dbgs() << " Removed VCMP: "; in ReplaceVCMPsByVPNOTs()
990 dbgs() << " with VMOVT: "; MIBuilder.getInstr()->dump()); in ConvertVPSEL()
/netbsd-src/external/apache2/llvm/dist/llvm/tools/llvm-exegesis/lib/Mips/
H A DTarget.cpp44 const auto Op = IT.getInstr().Operands[OpIdx]; in setMemOp()
140 assert(!isInvalidMemoryInstr(IT.getInstr()) && in fillMemoryOperands()

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