| /netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/ |
| H A D | LiveStacks.cpp | 70 S2RCMap[Slot] = TRI->getCommonSubClass(OldRC, RC); in getOrCreateInterval()
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| H A D | TargetRegisterInfo.cpp | 288 TargetRegisterInfo::getCommonSubClass(const TargetRegisterClass *A, in getCommonSubClass() function in TargetRegisterInfo
409 return TRI.getCommonSubClass(DefRC, SrcRC) != nullptr; in shareSameRegisterFile()
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| H A D | DetectDeadLanes.cpp | 187 return !TRI.getCommonSubClass(SrcRC, DstRC); in isCrossCopy()
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| H A D | MachineRegisterInfo.cpp | 75 MRI.getTargetRegisterInfo()->getCommonSubClass(OldRC, RC); in constrainRegClass()
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| H A D | RegisterCoalescer.cpp | 501 NewRC = TRI.getCommonSubClass(DstRC, SrcRC); in setRegisters()
1353 TRI->getCommonSubClass(DefRC, DstRC); in reMaterializeTrivialDef()
1406 NewRC = TRI->getCommonSubClass(NewRC, DefRC); in reMaterializeTrivialDef()
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| H A D | MachineInstr.cpp | 962 CurRC = TRI->getCommonSubClass(CurRC, OpRC); in getRegClassConstraintEffect()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/SystemZ/ |
| H A D | SystemZRegisterInfo.cpp | 151 TRI->getCommonSubClass(getRC32(FalseMO, VRM, MRI), in getRegAllocationHints()
154 RC = TRI->getCommonSubClass(RC, in getRegAllocationHints()
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| H A D | SystemZInstrInfo.cpp | 548 RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg)); in canInsertSelect()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
| H A D | SIRegisterInfo.cpp | 2082 return getCommonSubClass(&AMDGPU::VGPR_LO16RegClass, RC) != nullptr || in hasVGPRs()
2083 getCommonSubClass(&AMDGPU::VGPR_HI16RegClass, RC) != nullptr; in hasVGPRs()
2090 return getCommonSubClass(VRC, RC) != nullptr; in hasVGPRs()
2102 return getCommonSubClass(ARC, RC) != nullptr; in hasAGPRs()
2192 return getCommonSubClass(DefRC, SrcRC) != nullptr; in shouldRewriteCopySrc()
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| H A D | SIInstrInfo.cpp | 4518 if (RI.getCommonSubClass(VRC64, VRC)) in legalizeOpWithMove()
5550 if (RI.getCommonSubClass(MRI.getRegClass(Rsrc->getReg()), in legalizeOperands()
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| /netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/ |
| H A D | TargetRegisterInfo.h | 750 getCommonSubClass(const TargetRegisterClass *A,
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | InstrEmitter.cpp | 145 TRI->getCommonSubClass(UseRC, RC); in EmitCopyFromReg()
222 VTRC = TRI->getCommonSubClass(RC, VTRC); in CreateVirtualRegisters()
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| H A D | DAGCombiner.cpp | 16048 if (!TRI || TRI->getCommonSubClass(ArgRC, ResRC)) in canMergeExpensiveCrossRegisterBankCopy()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/ |
| H A D | PPCInstrInfo.cpp | 1547 RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg)); in canInsertSelect()
1580 RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg)); in insertSelect()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/ |
| H A D | AArch64InstrInfo.cpp | 620 RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg)); in canInsertSelect()
627 if (!RI.getCommonSubClass(RC, MRI.getRegClass(DstReg))) in canInsertSelect()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/X86/ |
| H A D | X86InstrInfo.cpp | 3323 RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg)); in canInsertSelect()
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