| /netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/ |
| H A D | MachineInstr.h | 1387 return findRegisterDefOperandIdx(Reg, false, false, TRI) != -1;
1395 return findRegisterDefOperandIdx(Reg, false, true, TRI) != -1;
1403 return findRegisterDefOperandIdx(Reg, true, false, TRI) != -1;
1437 int findRegisterDefOperandIdx(Register Reg,
1447 int Idx = findRegisterDefOperandIdx(Reg, isDead, Overlap, TRI);
|
| /netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/ |
| H A D | MachineCombiner.cpp | 200 int DefIdx = DefInstr->findRegisterDefOperandIdx(MO.getReg()); in getDepth()
209 DefInstr, DefInstr->findRegisterDefOperandIdx(MO.getReg()), in getDepth()
253 NewRoot, NewRoot->findRegisterDefOperandIdx(MO.getReg()), UseMO, in getLatency()
|
| H A D | EarlyIfConversion.cpp | 598 int TIdx = TDef->findRegisterDefOperandIdx(TReg); in hasSameValue()
599 int FIdx = FDef->findRegisterDefOperandIdx(FReg); in hasSameValue()
|
| H A D | AggressiveAntiDepBreaker.cpp | 698 int Idx = UseMI->findRegisterDefOperandIdx(NewReg, false, true, TRI); in FindSuitableFreeRegisters()
|
| H A D | ModuloSchedule.cpp | 1663 assert(Def->findRegisterDefOperandIdx(MI.getOperand(1).getReg()) != -1); in moveStageBetweenBlocks()
1889 unsigned OpIdx = MI->findRegisterDefOperandIdx(Reg); in getEquivalentRegisterIn()
|
| H A D | TwoAddressInstructionPass.cpp | 1241 unsigned NewDstIdx = NewMIs[1]->findRegisterDefOperandIdx(regA); in tryInstructionTransform()
|
| H A D | MachineInstr.cpp | 1041 MachineInstr::findRegisterDefOperandIdx(Register Reg, bool isDead, bool Overlap, in findRegisterDefOperandIdx() function in MachineInstr
|
| H A D | RegisterCoalescer.cpp | 834 int DefIdx = DefMI->findRegisterDefOperandIdx(IntA.reg()); in removeCopyByCommutingDef()
|
| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64PostSelectOptimize.cpp | 144 int DeadNZCVIdx = II.findRegisterDefOperandIdx(AArch64::NZCV); in optimizeNZCVDefs()
|
| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/ |
| H A D | AArch64InstrInfo.cpp | 559 if (DefMI->findRegisterDefOperandIdx(AArch64::NZCV, true) == -1) in canFoldIntoCSel()
587 if (DefMI->findRegisterDefOperandIdx(AArch64::NZCV, true) == -1) in canFoldIntoCSel()
1442 int DeadNZCVIdx = CmpInstr.findRegisterDefOperandIdx(AArch64::NZCV, true); in optimizeCompareInstr()
1776 if (MI.findRegisterDefOperandIdx(AArch64::NZCV, true) != -1) in canCmpInstrBeRemoved()
4582 int Cmp_NZCV = Root.findRegisterDefOperandIdx(AArch64::NZCV, true); in getMaddPatterns()
6184 if (DefMI->findRegisterDefOperandIdx(AArch64::NZCV, true) != -1) in optimizeCondBranch()
|
| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARM/ |
| H A D | ARMLowOverheadLoops.cpp | 88 return MI->findRegisterDefOperandIdx(ARM::VPR) != -1; in isVectorPredicate()
|
| H A D | ARMBaseInstrInfo.cpp | 1705 int ImpDefIdx = MI.findRegisterDefOperandIdx(DstRegD); in expandPostRAPseudo()
4108 Idx = II->findRegisterDefOperandIdx(Reg, false, true, TRI); in getBundledDefMI()
|
| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
| H A D | R600InstrInfo.cpp | 212 return MI.findRegisterDefOperandIdx(R600::AR_X, false, false, &RI) != -1; in definesAddressRegister()
|
| H A D | SIInstrInfo.cpp | 6120 if (CandI.findRegisterDefOperandIdx(AMDGPU::SCC, false, false, &RI) != in lowerSelect()
6802 if (MI.findRegisterDefOperandIdx(AMDGPU::SCC, false, false, &RI) != -1) in addSCCDefUsersToVALUWorklist()
|
| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/ |
| H A D | HexagonInstrInfo.cpp | 4233 int Idx = DefMI.findRegisterDefOperandIdx(*SR, false, false, &HRI); in getOperandLatency()
|