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Searched refs:fb_div (Results 1 – 23 of 23) sorted by relevance

/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
H A Damdgpu_pll.c92 unsigned *fb_div, unsigned *ref_div) in amdgpu_pll_get_fb_ref_div() argument
99 *fb_div = DIV_ROUND_CLOSEST(nom * *ref_div * post_div, den); in amdgpu_pll_get_fb_ref_div()
102 if (*fb_div > fb_div_max) { in amdgpu_pll_get_fb_ref_div()
103 *ref_div = DIV_ROUND_CLOSEST(*ref_div * fb_div_max, *fb_div); in amdgpu_pll_get_fb_ref_div()
104 *fb_div = fb_div_max; in amdgpu_pll_get_fb_ref_div()
132 unsigned fb_div_min, fb_div_max, fb_div; in amdgpu_pll_compute() local
209 ref_div_max, &fb_div, &ref_div); in amdgpu_pll_compute()
210 diff = abs(target_clock - (pll->reference_freq * fb_div) / in amdgpu_pll_compute()
224 &fb_div, &ref_div); in amdgpu_pll_compute()
228 amdgpu_pll_reduce_ratio(&fb_div, &ref_div, fb_div_min, ref_div_min); in amdgpu_pll_compute()
[all …]
H A Damdgpu_atombios_crtc.c589 u32 fb_div, in amdgpu_atombios_crtc_program_pll() argument
616 args.v1.usFbDiv = cpu_to_le16(fb_div); in amdgpu_atombios_crtc_program_pll()
626 args.v2.usFbDiv = cpu_to_le16(fb_div); in amdgpu_atombios_crtc_program_pll()
636 args.v3.usFbDiv = cpu_to_le16(fb_div); in amdgpu_atombios_crtc_program_pll()
653 args.v5.usFbDiv = cpu_to_le16(fb_div); in amdgpu_atombios_crtc_program_pll()
683 args.v6.usFbDiv = cpu_to_le16(fb_div); in amdgpu_atombios_crtc_program_pll()
832 u32 ref_div = 0, fb_div = 0, frac_fb_div = 0, post_div = 0; in amdgpu_atombios_crtc_set_pll() local
861 &fb_div, &frac_fb_div, &ref_div, &post_div); in amdgpu_atombios_crtc_set_pll()
868 ref_div, fb_div, frac_fb_div, post_div, in amdgpu_atombios_crtc_set_pll()
874 u32 amount = (((fb_div * 10) + frac_fb_div) * in amdgpu_atombios_crtc_set_pll()
H A Damdgpu_atombios.h43 u32 fb_div; member
68 u32 fb_div; member
H A Datombios_crtc.h51 u32 fb_div,
H A Damdgpu_si_dpm.c2957 u32 fb_div, p_div; in si_init_smc_spll_table() local
2976 fb_div = (sclk_params.vCG_SPLL_FUNC_CNTL_3 & SPLL_FB_DIV_MASK) >> SPLL_FB_DIV_SHIFT; in si_init_smc_spll_table()
2980 fb_div &= ~0x00001FFF; in si_init_smc_spll_table()
2981 fb_div >>= 1; in si_init_smc_spll_table()
2986 if (fb_div & ~(SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_SHIFT)) in si_init_smc_spll_table()
2996 …tmp = ((fb_div << SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_MAS… in si_init_smc_spll_table()
/netbsd-src/sys/external/bsd/drm2/dist/drm/radeon/
H A Dradeon_clocks.c48 uint32_t fb_div, ref_div, post_div, sclk; in radeon_legacy_get_engine_clock() local
50 fb_div = RREG32_PLL(RADEON_M_SPLL_REF_FB_DIV); in radeon_legacy_get_engine_clock()
51 fb_div = (fb_div >> RADEON_SPLL_FB_DIV_SHIFT) & RADEON_SPLL_FB_DIV_MASK; in radeon_legacy_get_engine_clock()
52 fb_div <<= 1; in radeon_legacy_get_engine_clock()
53 fb_div *= spll->reference_freq; in radeon_legacy_get_engine_clock()
61 sclk = fb_div / ref_div; in radeon_legacy_get_engine_clock()
78 uint32_t fb_div, ref_div, post_div, mclk; in radeon_legacy_get_memory_clock() local
80 fb_div = RREG32_PLL(RADEON_M_SPLL_REF_FB_DIV); in radeon_legacy_get_memory_clock()
81 fb_div = (fb_div >> RADEON_MPLL_FB_DIV_SHIFT) & RADEON_MPLL_FB_DIV_MASK; in radeon_legacy_get_memory_clock()
82 fb_div <<= 1; in radeon_legacy_get_memory_clock()
[all …]
H A Dradeon_display.c924 unsigned *fb_div, unsigned *ref_div) in avivo_get_fb_ref_div() argument
931 *fb_div = DIV_ROUND_CLOSEST(nom * *ref_div * post_div, den); in avivo_get_fb_ref_div()
934 if (*fb_div > fb_div_max) { in avivo_get_fb_ref_div()
935 *ref_div = (*ref_div * fb_div_max)/(*fb_div); in avivo_get_fb_ref_div()
936 *fb_div = fb_div_max; in avivo_get_fb_ref_div()
964 unsigned fb_div_min, fb_div_max, fb_div; in radeon_compute_pll_avivo() local
1044 ref_div_max, &fb_div, &ref_div); in radeon_compute_pll_avivo()
1045 diff = abs(target_clock - (pll->reference_freq * fb_div) / in radeon_compute_pll_avivo()
1059 &fb_div, &ref_div); in radeon_compute_pll_avivo()
1063 avivo_reduce_ratio(&fb_div, &ref_div, fb_div_min, ref_div_min); in radeon_compute_pll_avivo()
[all …]
H A Dradeon_rs780_dpm.c93 r600_engine_clock_entry_set_feedback_divider(rdev, 0, dividers.fb_div); in rs780_initialize_dpm_power_state()
411 static void rs780_force_fbdiv(struct radeon_device *rdev, u32 fb_div) in rs780_force_fbdiv() argument
420 WREG32_P(FVTHROT_FBDIV_REG2, FORCED_FEEDBACK_DIV(fb_div), in rs780_force_fbdiv()
422 WREG32_P(FVTHROT_FBDIV_REG1, STARTING_FEEDBACK_DIV(fb_div), in rs780_force_fbdiv()
465 rs780_force_fbdiv(rdev, max_dividers.fb_div); in rs780_set_engine_clock_scaling()
467 if (max_dividers.fb_div > min_dividers.fb_div) { in rs780_set_engine_clock_scaling()
469 MIN_FEEDBACK_DIV(min_dividers.fb_div) | in rs780_set_engine_clock_scaling()
470 MAX_FEEDBACK_DIV(max_dividers.fb_div), in rs780_set_engine_clock_scaling()
1056 rs780_force_fbdiv(rdev, dividers.fb_div); in rs780_dpm_force_performance_level()
1063 rs780_force_fbdiv(rdev, dividers.fb_div); in rs780_dpm_force_performance_level()
H A Dradeon_atombios_crtc.c835 u32 fb_div, in atombios_crtc_program_pll() argument
862 args.v1.usFbDiv = cpu_to_le16(fb_div); in atombios_crtc_program_pll()
872 args.v2.usFbDiv = cpu_to_le16(fb_div); in atombios_crtc_program_pll()
882 args.v3.usFbDiv = cpu_to_le16(fb_div); in atombios_crtc_program_pll()
899 args.v5.usFbDiv = cpu_to_le16(fb_div); in atombios_crtc_program_pll()
928 args.v6.usFbDiv = cpu_to_le16(fb_div); in atombios_crtc_program_pll()
1077 u32 ref_div = 0, fb_div = 0, frac_fb_div = 0, post_div = 0; in atombios_crtc_set_pll() local
1109 &fb_div, &frac_fb_div, &ref_div, &post_div); in atombios_crtc_set_pll()
1112 &fb_div, &frac_fb_div, &ref_div, &post_div); in atombios_crtc_set_pll()
1115 &fb_div, &frac_fb_div, &ref_div, &post_div); in atombios_crtc_set_pll()
[all …]
H A Dradeon_uvd.c985 uint64_t fb_div = (uint64_t)vco_freq * fb_factor; in radeon_uvd_calc_upll_dividers() local
988 do_div(fb_div, ref_freq); in radeon_uvd_calc_upll_dividers()
991 if (fb_div > fb_mask) in radeon_uvd_calc_upll_dividers()
994 fb_div &= fb_mask; in radeon_uvd_calc_upll_dividers()
1013 *optimal_fb_div = fb_div; in radeon_uvd_calc_upll_dividers()
H A Dradeon_rv730_dpm.c164 mpll_func_cntl_3 |= MPLL_FB_DIV(dividers.fb_div); in rv730_populate_mclk_value()
178 u32 clk_v = ss.percentage * dividers.fb_div / (clk_s * 10000); in rv730_populate_mclk_value()
H A Dradeon_rv770.c58 unsigned fb_div = 0, vclk_div = 0, dclk_div = 0; in rv770_set_uvd_clocks() local
78 &fb_div, &vclk_div, &dclk_div); in rv770_set_uvd_clocks()
82 fb_div |= 1; in rv770_set_uvd_clocks()
112 WREG32_P(CG_UPLL_FUNC_CNTL_3, UPLL_FB_DIV(fb_div), in rv770_set_uvd_clocks()
H A Dradeon_mode.h594 u32 fb_div; member
619 u32 fb_div; member
H A Dradeon_legacy_crtc.c272 uint16_t fb_div) in radeon_compute_pll_gain() argument
279 vcoFreq = ((unsigned)ref_freq * fb_div) / ref_div; in radeon_compute_pll_gain()
H A Dradeon_si.c7013 unsigned fb_div = 0, vclk_div = 0, dclk_div = 0; in si_set_uvd_clocks() local
7031 &fb_div, &vclk_div, &dclk_div); in si_set_uvd_clocks()
7060 WREG32_P(CG_UPLL_FUNC_CNTL_3, UPLL_FB_DIV(fb_div), ~UPLL_FB_DIV_MASK); in si_set_uvd_clocks()
7065 if (fb_div < 307200) in si_set_uvd_clocks()
7525 unsigned fb_div = 0, evclk_div = 0, ecclk_div = 0; in si_set_vce_clocks() local
7546 &fb_div, &evclk_div, &ecclk_div); in si_set_vce_clocks()
7578 WREG32_SMC_P(CG_VCEPLL_FUNC_CNTL_3, VCEPLL_FB_DIV(fb_div), ~VCEPLL_FB_DIV_MASK); in si_set_vce_clocks()
H A Dradeon_ni_dpm.c2100 u32 fb_div; in ni_init_smc_spll_table() local
2121 fb_div = (sclk_params.vCG_SPLL_FUNC_CNTL_3 & SPLL_FB_DIV_MASK) >> SPLL_FB_DIV_SHIFT; in ni_init_smc_spll_table()
2125 fb_div &= ~0x00001FFF; in ni_init_smc_spll_table()
2126 fb_div >>= 1; in ni_init_smc_spll_table()
2144 …tmp = ((fb_div << SMC_NISLANDS_SPLL_DIV_TABLE_FBDIV_SHIFT) & SMC_NISLANDS_SPLL_DIV_TABLE_FBDIV_MAS… in ni_init_smc_spll_table()
H A Dradeon_r600.c212 unsigned fb_div = 0, ref_div, vclk_div = 0, dclk_div = 0; in r600_set_uvd_clocks() local
241 &fb_div, &vclk_div, &dclk_div); in r600_set_uvd_clocks()
246 fb_div >>= 1; in r600_set_uvd_clocks()
248 fb_div |= 1; in r600_set_uvd_clocks()
264 UPLL_FB_DIV(fb_div) | in r600_set_uvd_clocks()
H A Dradeon_si_dpm.c2857 u32 fb_div, p_div; in si_init_smc_spll_table() local
2877 fb_div = (sclk_params.vCG_SPLL_FUNC_CNTL_3 & SPLL_FB_DIV_MASK) >> SPLL_FB_DIV_SHIFT; in si_init_smc_spll_table()
2881 fb_div &= ~0x00001FFF; in si_init_smc_spll_table()
2882 fb_div >>= 1; in si_init_smc_spll_table()
2887 if (fb_div & ~(SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_SHIFT)) in si_init_smc_spll_table()
2897 …tmp = ((fb_div << SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_MAS… in si_init_smc_spll_table()
H A Dradeon_rv6xx_dpm.c534 return ref_clock * ((dividers->fb_div & ~1) << fb_divider_scale) / in rv6xx_calculate_vco_frequency()
612 rv6xx_memory_clock_entry_set_feedback_divider(rdev, entry, dividers.fb_div); in rv6xx_program_mclk_stepping_entry()
H A Dradeon_evergreen.c1200 unsigned fb_div = 0, vclk_div = 0, dclk_div = 0; in evergreen_set_uvd_clocks() local
1219 &fb_div, &vclk_div, &dclk_div); in evergreen_set_uvd_clocks()
1246 WREG32_P(CG_UPLL_FUNC_CNTL_3, UPLL_FB_DIV(fb_div), ~UPLL_FB_DIV_MASK); in evergreen_set_uvd_clocks()
1251 if (fb_div < 307200) in evergreen_set_uvd_clocks()
H A Dradeon_atombios.c2857 dividers->fb_div = args.v1.ucFbDiv; in radeon_atom_get_clock_dividers()
2871 dividers->fb_div = le16_to_cpu(args.v2.usFbDiv); in radeon_atom_get_clock_dividers()
2878 dividers->enable_post_div = (dividers->fb_div & 1) ? true : false; in radeon_atom_get_clock_dividers()
H A Dradeon_ci_dpm.c3187 fbdiv = dividers.fb_div & 0x3FFFFFF; in ci_calculate_sclk_params()
/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce/
H A Damdgpu_dce_clock_source.c656 struct fixed31_32 fb_div; in calculate_ss() local
676 fb_div = dc_fixpt_from_fraction( in calculate_ss()
678 fb_div = dc_fixpt_add_int(fb_div, pll_settings->feedback_divider); in calculate_ss()
684 fb_div, dc_fixpt_from_fraction(ss_data->percentage, in calculate_ss()