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Searched refs:engine_mask (Results 1 – 18 of 18) sorted by relevance

/netbsd-src/sys/external/bsd/drm2/dist/drm/i915/gt/
H A Dintel_reset.c182 intel_engine_mask_t engine_mask, in i915_do_reset() argument
211 intel_engine_mask_t engine_mask, in g33_do_reset() argument
221 intel_engine_mask_t engine_mask, in g4x_do_reset() argument
257 static int ilk_do_reset(struct intel_gt *gt, intel_engine_mask_t engine_mask, in ilk_do_reset() argument
317 intel_engine_mask_t engine_mask, in gen6_reset_engines() argument
330 if (engine_mask == ALL_ENGINES) { in gen6_reset_engines()
336 for_each_engine_masked(engine, gt, engine_mask, tmp) { in gen6_reset_engines()
448 intel_engine_mask_t engine_mask, in gen11_reset_engines() argument
466 if (engine_mask == ALL_ENGINES) { in gen11_reset_engines()
470 for_each_engine_masked(engine, gt, engine_mask, tmp) { in gen11_reset_engines()
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H A Dintel_reset.h29 intel_engine_mask_t engine_mask,
55 int __intel_gt_reset(struct intel_gt *gt, intel_engine_mask_t engine_mask);
H A Dintel_gt.h52 intel_engine_mask_t engine_mask);
H A Dintel_engine_cs.c436 const unsigned int engine_mask = INTEL_INFO(i915)->engine_mask; in intel_engines_init_mmio() local
441 WARN_ON(engine_mask == 0); in intel_engines_init_mmio()
442 WARN_ON(engine_mask & in intel_engines_init_mmio()
464 if (WARN_ON(mask != engine_mask)) in intel_engines_init_mmio()
465 device_info->engine_mask = mask; in intel_engines_init_mmio()
H A Dintel_gt.c159 intel_engine_mask_t engine_mask) in intel_gt_clear_error_registers() argument
196 for_each_engine_masked(engine, gt, engine_mask, id) in intel_gt_clear_error_registers()
/netbsd-src/sys/external/bsd/drm2/dist/drm/i915/
H A Di915_pci.c174 .engine_mask = BIT(RCS0), \
192 .engine_mask = BIT(RCS0), \
227 .engine_mask = BIT(RCS0), \
313 .engine_mask = BIT(RCS0), \
344 .engine_mask = BIT(RCS0) | BIT(VCS0),
354 .engine_mask = BIT(RCS0) | BIT(VCS0),
362 .engine_mask = BIT(RCS0) | BIT(VCS0), \
390 .engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), \
439 .engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), \
506 .engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0),
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H A Dintel_device_info.h159 intel_engine_mask_t engine_mask; /* Engines supported by the HW */ member
H A Dintel_device_info.c95 drm_printf(p, "engines: %x\n", info->engine_mask); in intel_device_info_print_static()
1091 info->engine_mask &= ~BIT(_VCS(i)); in intel_device_info_init_mmio()
1115 info->engine_mask &= ~BIT(_VECS(i)); in intel_device_info_init_mmio()
H A Di915_drv.h1372 for ((tmp__) = (mask__) & INTEL_INFO((gt__)->i915)->engine_mask; \
1651 #define HAS_ENGINE(dev_priv, id) (INTEL_INFO(dev_priv)->engine_mask & BIT(id))
1656 (INTEL_INFO(dev_priv)->engine_mask & \
/netbsd-src/sys/external/bsd/drm2/dist/drm/i915/gvt/
H A Dscheduler.h148 intel_engine_mask_t engine_mask);
153 intel_engine_mask_t engine_mask,
166 intel_engine_mask_t engine_mask);
H A Dexeclist.c535 intel_engine_mask_t engine_mask) in clean_execlist() argument
542 for_each_engine_masked(engine, &dev_priv->gt, engine_mask, tmp) { in clean_execlist()
550 intel_engine_mask_t engine_mask) in reset_execlist() argument
556 for_each_engine_masked(engine, &dev_priv->gt, engine_mask, tmp) in reset_execlist()
561 intel_engine_mask_t engine_mask) in init_execlist() argument
563 reset_execlist(vgpu, engine_mask); in init_execlist()
H A Dvgpu.c534 intel_engine_mask_t engine_mask) in intel_gvt_reset_vgpu_locked() argument
538 intel_engine_mask_t resetting_eng = dmlr ? ALL_ENGINES : engine_mask; in intel_gvt_reset_vgpu_locked()
542 vgpu->id, dmlr, engine_mask); in intel_gvt_reset_vgpu_locked()
559 if (engine_mask == ALL_ENGINES || dmlr) { in intel_gvt_reset_vgpu_locked()
H A Dscheduler.c874 intel_engine_mask_t engine_mask) in intel_vgpu_clean_workloads() argument
883 for_each_engine_masked(engine, &dev_priv->gt, engine_mask, tmp) { in intel_vgpu_clean_workloads()
1184 intel_engine_mask_t engine_mask) in intel_vgpu_reset_submission() argument
1191 intel_vgpu_clean_workloads(vgpu, engine_mask); in intel_vgpu_reset_submission()
1192 s->ops->reset(vgpu, engine_mask); in intel_vgpu_reset_submission()
1314 intel_engine_mask_t engine_mask, in intel_vgpu_select_submission_ops() argument
1327 if (WARN_ON(interface == 0 && engine_mask != ALL_ENGINES)) in intel_vgpu_select_submission_ops()
1331 s->ops->clean(vgpu, engine_mask); in intel_vgpu_select_submission_ops()
1341 ret = ops[interface]->init(vgpu, engine_mask); in intel_vgpu_select_submission_ops()
H A Dgvt.h146 int (*init)(struct intel_vgpu *vgpu, intel_engine_mask_t engine_mask);
147 void (*clean)(struct intel_vgpu *vgpu, intel_engine_mask_t engine_mask);
148 void (*reset)(struct intel_vgpu *vgpu, intel_engine_mask_t engine_mask);
490 intel_engine_mask_t engine_mask);
H A Dexeclist.h187 intel_engine_mask_t engine_mask);
H A Dhandlers.c319 intel_engine_mask_t engine_mask = 0; in gdrst_mmio_write() local
327 engine_mask = ALL_ENGINES; in gdrst_mmio_write()
331 engine_mask |= BIT(RCS0); in gdrst_mmio_write()
335 engine_mask |= BIT(VCS0); in gdrst_mmio_write()
339 engine_mask |= BIT(BCS0); in gdrst_mmio_write()
343 engine_mask |= BIT(VECS0); in gdrst_mmio_write()
347 engine_mask |= BIT(VCS1); in gdrst_mmio_write()
353 engine_mask &= INTEL_INFO(vgpu->gvt->dev_priv)->engine_mask; in gdrst_mmio_write()
357 intel_gvt_reset_vgpu_locked(vgpu, false, engine_mask); in gdrst_mmio_write()
/netbsd-src/sys/external/bsd/drm2/dist/drm/i915/selftests/
H A Dmock_gem_device.c185 mkwrite_device_info(i915)->engine_mask = BIT(0); in mock_gem_device()
/netbsd-src/sys/external/bsd/drm2/dist/drm/i915/gem/
H A Di915_gem_execbuffer.c2259 return hweight64(INTEL_INFO(i915)->engine_mask & in num_vcs_engines()