| /netbsd-src/sys/external/bsd/drm2/dist/drm/radeon/ |
| H A D | rv770_dpm.h | 183 u32 engine_clock,
186 u32 engine_clock, u32 memory_clock,
204 int rv740_populate_sclk_value(struct radeon_device *rdev, u32 engine_clock,
207 u32 engine_clock, u32 memory_clock,
229 u32 engine_clock);
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| H A D | radeon_rv740_dpm.c | 125 int rv740_populate_sclk_value(struct radeon_device *rdev, u32 engine_clock, in rv740_populate_sclk_value() argument
142 engine_clock, false, ÷rs); in rv740_populate_sclk_value()
148 tmp = (u64) engine_clock * reference_divider * dividers.post_div * 16384; in rv740_populate_sclk_value()
165 u32 vco_freq = engine_clock * dividers.post_div; in rv740_populate_sclk_value()
181 sclk->sclk_value = cpu_to_be32(engine_clock); in rv740_populate_sclk_value()
192 u32 engine_clock, u32 memory_clock, in rv740_populate_mclk_value() argument
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| H A D | radeon_rv730_dpm.c | 45 u32 engine_clock, in rv730_populate_sclk_value() argument
62 engine_clock, false, ÷rs); in rv730_populate_sclk_value()
74 tmp = (u64) engine_clock * reference_divider * post_divider * 16384; in rv730_populate_sclk_value()
97 u32 vco_freq = engine_clock * post_divider; in rv730_populate_sclk_value()
113 sclk->sclk_value = cpu_to_be32(engine_clock); in rv730_populate_sclk_value()
124 u32 engine_clock, u32 memory_clock, in rv730_populate_mclk_value() argument
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| H A D | cypress_dpm.h | 127 u32 engine_clock, u32 memory_clock);
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| H A D | radeon_rv770_dpm.c | 391 u32 engine_clock, u32 memory_clock, in rv770_populate_mclk_value() argument
489 u32 engine_clock, in rv770_populate_sclk_value() argument
511 engine_clock, false, ÷rs); in rv770_populate_sclk_value()
522 tmp = (u64) engine_clock * reference_divider * post_divider * 16384; in rv770_populate_sclk_value()
544 u32 vco_freq = engine_clock * post_divider; in rv770_populate_sclk_value()
560 sclk->sclk_value = cpu_to_be32(engine_clock); in rv770_populate_sclk_value()
727 u32 engine_clock) in rv770_calculate_memory_refresh_rate() argument
738 mc_arb_rfsh_rate = ((engine_clock * 10) * dram_refresh_rate / dram_rows - 32) / 64; in rv770_calculate_memory_refresh_rate()
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| H A D | radeon_ci_dpm.c | 2502 const u32 engine_clock, in ci_register_patching_mc_arb() argument
2516 tmp2 = (((0x31 * engine_clock) / 125000) - 1) & 0xff; in ci_register_patching_mc_arb()
2520 tmp2 = (((0x36 * engine_clock) / 137500) - 1) & 0xff; in ci_register_patching_mc_arb()
3166 u32 engine_clock, in ci_calculate_sclk_params() argument
3182 engine_clock, false, ÷rs); in ci_calculate_sclk_params()
3195 u32 vco_freq = engine_clock * dividers.post_div; in ci_calculate_sclk_params()
3211 sclk->SclkFrequency = engine_clock; in ci_calculate_sclk_params()
3222 u32 engine_clock, in ci_populate_single_graphic_level() argument
3229 ret = ci_calculate_sclk_params(rdev, engine_clock, graphic_level); in ci_populate_single_graphic_level()
3235 engine_clock, &graphic_level->MinVddc); in ci_populate_single_graphic_level()
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| H A D | radeon_ni_dpm.c | 2003 u32 engine_clock, in ni_calculate_sclk_params() argument
2022 engine_clock, false, ÷rs); in ni_calculate_sclk_params()
2029 tmp = (u64) engine_clock * reference_divider * dividers.post_div * 16834; in ni_calculate_sclk_params()
2046 u32 vco_freq = engine_clock * dividers.post_div; in ni_calculate_sclk_params()
2062 sclk->sclk_value = engine_clock; in ni_calculate_sclk_params()
2074 u32 engine_clock, in ni_populate_sclk_value() argument
2080 ret = ni_calculate_sclk_params(rdev, engine_clock, &sclk_tmp); in ni_populate_sclk_value()
2165 u32 engine_clock, in ni_populate_mclk_value() argument
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| H A D | radeon_si_dpm.c | 1763 u32 engine_clock,
4278 u32 engine_clock) in si_calculate_memory_refresh_rate() argument
4291 mc_arb_rfsh_rate = ((engine_clock * 10) * dram_refresh_rate / dram_rows - 32) / 64; in si_calculate_memory_refresh_rate()
4786 u32 engine_clock, in si_calculate_sclk_params() argument
4805 engine_clock, false, ÷rs); in si_calculate_sclk_params()
4811 tmp = (u64) engine_clock * reference_divider * dividers.post_div * 16384; in si_calculate_sclk_params()
4828 u32 vco_freq = engine_clock * dividers.post_div; in si_calculate_sclk_params()
4844 sclk->sclk_value = engine_clock; in si_calculate_sclk_params()
4856 u32 engine_clock, in si_populate_sclk_value() argument
4862 ret = si_calculate_sclk_params(rdev, engine_clock, &sclk_tmp); in si_populate_sclk_value()
[all …]
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| H A D | radeon_cypress_dpm.c | 480 u32 engine_clock, u32 memory_clock, in cypress_populate_mclk_value() argument
910 u32 engine_clock, u32 memory_clock) in cypress_calculate_burst_time() argument
914 u32 result = (4 * multiplier * engine_clock) / (memory_clock / 2); in cypress_calculate_burst_time()
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| H A D | radeon_rv6xx_dpm.c | 787 u32 engine_clock) in calculate_memory_refresh_rate() argument
796 return ((engine_clock * 10) * dram_refresh_rate / dram_rows - 32) / 64; in calculate_memory_refresh_rate()
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| /netbsd-src/sys/external/bsd/drm2/dist/drm/amd/powerplay/hwmgr/ |
| H A D | amdgpu_smu7_hwmgr.c | 2926 if (smu7_ps->performance_levels[i].engine_clock > max_limits->sclk) in smu7_apply_state_adjust_rules()
2927 smu7_ps->performance_levels[i].engine_clock = max_limits->sclk; in smu7_apply_state_adjust_rules()
2971 sclk = smu7_ps->performance_levels[0].engine_clock; in smu7_apply_state_adjust_rules()
2986 smu7_ps->performance_levels[0].engine_clock = sclk; in smu7_apply_state_adjust_rules()
2989 smu7_ps->performance_levels[1].engine_clock = in smu7_apply_state_adjust_rules()
2990 (smu7_ps->performance_levels[1].engine_clock >= in smu7_apply_state_adjust_rules()
2991 smu7_ps->performance_levels[0].engine_clock) ? in smu7_apply_state_adjust_rules()
2992 smu7_ps->performance_levels[1].engine_clock : in smu7_apply_state_adjust_rules()
2993 smu7_ps->performance_levels[0].engine_clock; in smu7_apply_state_adjust_rules()
3011 smu7_ps->performance_levels[i].engine_clock = stable_pstate_sclk; in smu7_apply_state_adjust_rules()
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| H A D | ppatomctrl.h | 297 …t_engine_clock_spread_spectrum(struct pp_hwmgr *hwmgr, const uint32_t engine_clock, pp_atomctrl_in…
299 extern int atomctrl_set_engine_dram_timings_rv770(struct pp_hwmgr *hwmgr, uint32_t engine_clock, ui…
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| H A D | smu10_hwmgr.h | 78 uint32_t engine_clock; member
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| H A D | smu7_hwmgr.h | 58 uint32_t engine_clock; member
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| H A D | amdgpu_smu10_hwmgr.c | 762 smu10_ps->levels[index].engine_clock = 0; in smu10_dpm_get_pp_table_entry_callback()
968 clock_info->min_eng_clk = ps->levels[0].engine_clock / (1 << (ps->levels[0].ss_divider_index)); in smu10_get_current_shallow_sleep_clocks()
969 …clock_info->max_eng_clk = ps->levels[ps->level - 1].engine_clock / (1 << (ps->levels[ps->level - 1… in smu10_get_current_shallow_sleep_clocks()
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| H A D | amdgpu_ppatomctrl.c | 179 uint32_t engine_clock, in atomctrl_set_engine_dram_timings_rv770() argument
188 cpu_to_le32((engine_clock & SET_CLOCK_FREQ_MASK) | in atomctrl_set_engine_dram_timings_rv770()
1295 const uint32_t engine_clock, in atomctrl_get_engine_clock_spread_spectrum() argument
1299 ASIC_INTERNAL_ENGINE_SS, engine_clock, ssInfo); in atomctrl_get_engine_clock_spread_spectrum()
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| /netbsd-src/sys/external/bsd/drm2/dist/drm/amd/powerplay/smumgr/ |
| H A D | amdgpu_iceland_smumgr.c | 801 uint32_t engine_clock, SMU71_Discrete_GraphicsLevel *sclk) in iceland_calculate_sclk_params() argument
816 result = atomctrl_get_engine_pll_dividers_vi(hwmgr, engine_clock, ÷rs); in iceland_calculate_sclk_params()
847 uint32_t vcoFreq = engine_clock * dividers.uc_pll_post_div; in iceland_calculate_sclk_params()
868 sclk->SclkFrequency = engine_clock; in iceland_calculate_sclk_params()
897 uint32_t engine_clock, in iceland_populate_single_graphic_level() argument
903 result = iceland_calculate_sclk_params(hwmgr, engine_clock, graphic_level); in iceland_populate_single_graphic_level()
907 hwmgr->dyn_state.vddc_dependency_on_sclk, engine_clock, in iceland_populate_single_graphic_level()
913 graphic_level->SclkFrequency = engine_clock; in iceland_populate_single_graphic_level()
919 engine_clock, in iceland_populate_single_graphic_level()
942 smu7_get_sleep_divider_id_from_clock(engine_clock, in iceland_populate_single_graphic_level()
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| H A D | amdgpu_tonga_smumgr.c | 544 uint32_t engine_clock, SMU72_Discrete_GraphicsLevel *sclk) in tonga_calculate_sclk_params() argument
559 result = atomctrl_get_engine_pll_dividers_vi(hwmgr, engine_clock, ÷rs); in tonga_calculate_sclk_params()
590 uint32_t vcoFreq = engine_clock * dividers.uc_pll_post_div; in tonga_calculate_sclk_params()
611 sclk->SclkFrequency = engine_clock; in tonga_calculate_sclk_params()
622 uint32_t engine_clock, in tonga_populate_single_graphic_level() argument
632 result = tonga_calculate_sclk_params(hwmgr, engine_clock, graphic_level); in tonga_populate_single_graphic_level()
641 vdd_dep_table, engine_clock, in tonga_populate_single_graphic_level()
648 graphic_level->SclkFrequency = engine_clock; in tonga_populate_single_graphic_level()
669 smu7_get_sleep_divider_id_from_clock(engine_clock, in tonga_populate_single_graphic_level()
1464 uint32_t engine_clock, in tonga_populate_memory_timing_parameters() argument
[all …]
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| H A D | amdgpu_ci_smumgr.c | 1626 uint32_t engine_clock, in ci_populate_memory_timing_parameters() argument
1637 engine_clock, memory_clock); in ci_populate_memory_timing_parameters()
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| /netbsd-src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/ |
| H A D | amdgpu_si_dpm.c | 1855 u32 engine_clock,
4744 u32 engine_clock) in si_calculate_memory_refresh_rate() argument
4757 mc_arb_rfsh_rate = ((engine_clock * 10) * dram_refresh_rate / dram_rows - 32) / 64; in si_calculate_memory_refresh_rate()
5250 u32 engine_clock, in si_calculate_sclk_params() argument
5269 engine_clock, false, ÷rs); in si_calculate_sclk_params()
5275 tmp = (u64) engine_clock * reference_divider * dividers.post_div * 16384; in si_calculate_sclk_params()
5292 u32 vco_freq = engine_clock * dividers.post_div; in si_calculate_sclk_params()
5308 sclk->sclk_value = engine_clock; in si_calculate_sclk_params()
5320 u32 engine_clock, in si_populate_sclk_value() argument
5326 ret = si_calculate_sclk_params(adev, engine_clock, &sclk_tmp); in si_populate_sclk_value()
[all …]
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| /netbsd-src/sys/external/bsd/drm2/dist/drm/amd/powerplay/inc/ |
| H A D | amdgpu_smu.h | 319 uint32_t engine_clock; member
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