Searched refs:engineClock (Results 1 – 14 of 14) sorted by relevance
215 hwmgr->platform_descriptor.overdriveLimit.engineClock = VEGA12_ENGINECLOCK_HARDMAX; in init_powerplay_table_information()217 hwmgr->platform_descriptor.overdriveLimit.engineClock = in init_powerplay_table_information()235 if (hwmgr->platform_descriptor.overdriveLimit.engineClock > 0 in init_powerplay_table_information()
422 data->boot_power_level.engineClock = in smu8_construct_boot_state()1321 return smu8_ps->levels[0].engineClock; in smu8_dpm_get_sclk()1323 return smu8_ps->levels[smu8_ps->level-1].engineClock; in smu8_dpm_get_sclk()1357 smu8_ps->levels[index].engineClock = table->entries[clock_info_index].clk; in smu8_dpm_get_pp_table_entry_callback()1574 level->coreClock = ps->levels[level_index].engineClock; in smu8_get_performance_level()1578 if (ps->levels[i].engineClock > data->dce_slow_sclk_threshold) { in smu8_get_performance_level()1579 level->coreClock = ps->levels[i].engineClock; in smu8_get_performance_level()1602 clock_info->min_eng_clk = ps->levels[0].engineClock / (1 << (ps->levels[0].ssDividerIndex)); in smu8_get_current_shallow_sleep_clocks()1603 …clock_info->max_eng_clk = ps->levels[ps->level - 1].engineClock / (1 << (ps->levels[ps->level - 1]… in smu8_get_current_shallow_sleep_clocks()
918 hwmgr->platform_descriptor.clockStep.engineClock = 500; in vega10_hwmgr_backend_init()1359 if (hwmgr->platform_descriptor.overdriveLimit.engineClock == 0) in vega10_setup_default_dpm_tables()1360 hwmgr->platform_descriptor.overdriveLimit.engineClock = in vega10_setup_default_dpm_tables()1570 hwmgr->platform_descriptor.overdriveLimit.engineClock; in vega10_populate_single_gfx_level()3218 minimum_clocks.engineClock = hwmgr->display_config->min_core_set_clock; in vega10_apply_state_adjust_rules()3249 minimum_clocks.engineClock = stable_pstate_sclk; in vega10_apply_state_adjust_rules()3271 if (sclk < minimum_clocks.engineClock) in vega10_apply_state_adjust_rules()3272 sclk = (minimum_clocks.engineClock > max_limits->sclk) ? in vega10_apply_state_adjust_rules()3273 max_limits->sclk : minimum_clocks.engineClock; in vega10_apply_state_adjust_rules()4638 hwmgr->platform_descriptor.overdriveLimit.engineClock/100); in vega10_print_clock_levels()[all …]
102 uint32_t engineClock; member
807 if (hwmgr->platform_descriptor.overdriveLimit.engineClock == 0) in smu7_setup_dpm_tables_v1()808 hwmgr->platform_descriptor.overdriveLimit.engineClock = dep_sclk_table->entries[i-1].clk; in smu7_setup_dpm_tables_v1()2595 hwmgr->platform_descriptor.clockStep.engineClock = 500; in smu7_hwmgr_backend_init()2931 minimum_clocks.engineClock = hwmgr->display_config->min_core_set_clock; in smu7_apply_state_adjust_rules()2954 minimum_clocks.engineClock = stable_pstate_sclk; in smu7_apply_state_adjust_rules()2978 if (sclk < minimum_clocks.engineClock) in smu7_apply_state_adjust_rules()2979 sclk = (minimum_clocks.engineClock > max_limits->sclk) ? in smu7_apply_state_adjust_rules()2980 max_limits->sclk : minimum_clocks.engineClock; in smu7_apply_state_adjust_rules()4535 hwmgr->platform_descriptor.overdriveLimit.engineClock/100); in smu7_print_clock_levels()4836 hwmgr->platform_descriptor.overdriveLimit.engineClock < clk) { in smu7_check_clk_voltage_valid()[all …]
999 hwmgr->platform_descriptor.overdriveLimit.engineClock = in init_overdrive_limits_V1_4()1037 hwmgr->platform_descriptor.overdriveLimit.engineClock = le32_to_cpu(header->ulMaxEngineClock); in init_overdrive_limits_V2_1()1057 hwmgr->platform_descriptor.overdriveLimit.engineClock = 0; in init_overdrive_limits()
332 hwmgr->platform_descriptor.overdriveLimit.engineClock = in init_over_drive_limits()335 hwmgr->platform_descriptor.overdriveLimit.engineClock = in init_over_drive_limits()
535 hwmgr->platform_descriptor.clockStep.engineClock = 500; in smu10_hwmgr_backend_init()
869 hwmgr->platform_descriptor.overdriveLimit.engineClock = in init_over_drive_limits()
429 hwmgr->platform_descriptor.clockStep.engineClock = 500; in vega12_hwmgr_backend_init()
474 hwmgr->platform_descriptor.clockStep.engineClock = 500; in vega20_hwmgr_backend_init()
329 uint32_t engineClock; member
773 unsigned int engineClock; member
2694 info->engineClock = (unsigned int)state->bw_ctx.bw.dcn.clk.dcfclk_khz; in get_clock_requirements_for_state()