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Searched refs:encode_pcie_lane_width (Results 1 – 9 of 9) sorted by relevance

/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/powerplay/hwmgr/
H A Dpppcielanes.h29 extern uint8_t encode_pcie_lane_width(uint32_t num_lanes);
H A Damdgpu_pppcielanes.c61 uint8_t encode_pcie_lane_width(uint32_t num_lanes) in encode_pcie_lane_width() function
H A Damdgpu_vega10_hwmgr.c1275 pcie_table->pcie_lane[i] = (uint8_t)encode_pcie_lane_width( in vega10_setup_default_pcie_table()
1278 pcie_table->pcie_lane[i] = (uint8_t)encode_pcie_lane_width( in vega10_setup_default_pcie_table()
/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/powerplay/smumgr/
H A Damdgpu_vegam_smumgr.c586 table->LinkLevel[i].PcieLaneCount = (uint8_t)encode_pcie_lane_width( in vegam_populate_smc_link_level()
H A Damdgpu_fiji_smumgr.c846 table->LinkLevel[i].PcieLaneCount = (uint8_t)encode_pcie_lane_width( in fiji_populate_smc_link_level()
H A Damdgpu_iceland_smumgr.c781 (uint8_t)encode_pcie_lane_width(dpm_table->pcie_speed_table.dpm_levels[i].param1); in iceland_populate_smc_link_level()
H A Damdgpu_polaris10_smumgr.c784 table->LinkLevel[i].PcieLaneCount = (uint8_t)encode_pcie_lane_width( in polaris10_populate_smc_link_level()
H A Damdgpu_ci_smumgr.c1012 (uint8_t)encode_pcie_lane_width(dpm_table->pcie_speed_table.dpm_levels[i].param1); in ci_populate_smc_link_level()
H A Damdgpu_tonga_smumgr.c524 (uint8_t)encode_pcie_lane_width(dpm_table->pcie_speed_table.dpm_levels[i].param1); in tonga_populate_smc_link_level()