Home
last modified time | relevance | path

Searched refs:dyn_state (Results 1 – 25 of 30) sorted by relevance

12

/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
H A Damdgpu_dpm.c339 ret = amdgpu_parse_clk_voltage_dep_table(&adev->pm.dpm.dyn_state.vddc_dependency_on_sclk, in amdgpu_parse_extended_power_table()
350 ret = amdgpu_parse_clk_voltage_dep_table(&adev->pm.dpm.dyn_state.vddci_dependency_on_mclk, in amdgpu_parse_extended_power_table()
361 ret = amdgpu_parse_clk_voltage_dep_table(&adev->pm.dpm.dyn_state.vddc_dependency_on_mclk, in amdgpu_parse_extended_power_table()
372 ret = amdgpu_parse_clk_voltage_dep_table(&adev->pm.dpm.dyn_state.mvdd_dependency_on_mclk, in amdgpu_parse_extended_power_table()
385 adev->pm.dpm.dyn_state.max_clock_voltage_on_dc.sclk = in amdgpu_parse_extended_power_table()
388 adev->pm.dpm.dyn_state.max_clock_voltage_on_dc.mclk = in amdgpu_parse_extended_power_table()
391 adev->pm.dpm.dyn_state.max_clock_voltage_on_dc.vddc = in amdgpu_parse_extended_power_table()
393 adev->pm.dpm.dyn_state.max_clock_voltage_on_dc.vddci = in amdgpu_parse_extended_power_table()
404 adev->pm.dpm.dyn_state.phase_shedding_limits_table.entries = in amdgpu_parse_extended_power_table()
408 if (!adev->pm.dpm.dyn_state.phase_shedding_limits_table.entries) { in amdgpu_parse_extended_power_table()
[all …]
H A Damdgpu_si_dpm.c2261 struct amdgpu_ppm_table *ppm = adev->pm.dpm.dyn_state.ppm_table; in si_populate_smc_tdp_limits()
2642 &adev->pm.dpm.dyn_state.cac_leakage_table; in si_get_cac_std_voltage_max_min()
3046 &adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table; in si_get_vce_clock_voltage()
3244 return btc_find_valid_clock(&adev->pm.dpm.dyn_state.valid_mclk_values, in btc_get_valid_mclk()
3251 return btc_find_valid_clock(&adev->pm.dpm.dyn_state.valid_sclk_values, in btc_get_valid_sclk()
3304 if (((pl->mclk + (pl->sclk - 1)) / pl->sclk) > adev->pm.dpm.dyn_state.mclk_sclk_ratio) in btc_adjust_clock_combinations()
3308 (adev->pm.dpm.dyn_state.mclk_sclk_ratio - 1)) / in btc_adjust_clock_combinations()
3309 adev->pm.dpm.dyn_state.mclk_sclk_ratio); in btc_adjust_clock_combinations()
3311 if ((pl->sclk - pl->mclk) > adev->pm.dpm.dyn_state.sclk_mclk_delta) in btc_adjust_clock_combinations()
3315 adev->pm.dpm.dyn_state.sclk_mclk_delta); in btc_adjust_clock_combinations()
[all …]
H A Damdgpu_kv_dpm.c81 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk; in kv_convert_vid2_to_vid7()
103 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk; in kv_convert_vid7_to_vid2()
808 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk; in kv_program_bootup_state()
910 &adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table; in kv_populate_uvd_table()
983 &adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table; in kv_populate_vce_table()
1044 &adev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table; in kv_populate_samu_table()
1110 &adev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table; in kv_populate_acp_table()
1169 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk; in kv_calculate_dfs_bypass_settings()
1502 &adev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table; in kv_update_uvd_dpm()
1538 &adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table; in kv_get_vce_boot_level()
[all …]
H A Damdgpu_dpm.h402 struct amdgpu_dpm_dynamic_state dyn_state; member
H A Damdgpu_atombios.c1368 u32 count = adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; in amdgpu_atombios_get_voltage_evv()
1372 if (adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[entry_id].v == in amdgpu_atombios_get_voltage_evv()
1384 cpu_to_le32(adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[entry_id].clk); in amdgpu_atombios_get_voltage_evv()
/netbsd-src/sys/external/bsd/drm2/dist/drm/radeon/
H A Dradeon_r600_dpm.c931 ret = r600_parse_clk_voltage_dep_table(&rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk, in r600_parse_extended_power_table()
940 ret = r600_parse_clk_voltage_dep_table(&rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk, in r600_parse_extended_power_table()
943 kfree(rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries); in r600_parse_extended_power_table()
951 ret = r600_parse_clk_voltage_dep_table(&rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk, in r600_parse_extended_power_table()
954 kfree(rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries); in r600_parse_extended_power_table()
955 kfree(rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk.entries); in r600_parse_extended_power_table()
963 ret = r600_parse_clk_voltage_dep_table(&rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk, in r600_parse_extended_power_table()
966 kfree(rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries); in r600_parse_extended_power_table()
967 kfree(rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk.entries); in r600_parse_extended_power_table()
968 kfree(rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk.entries); in r600_parse_extended_power_table()
[all …]
H A Dradeon_btc_dpm.c1236 return btc_find_valid_clock(&rdev->pm.dpm.dyn_state.valid_mclk_values, in btc_get_valid_mclk()
1243 return btc_find_valid_clock(&rdev->pm.dpm.dyn_state.valid_sclk_values, in btc_get_valid_sclk()
1286 if (((pl->mclk + (pl->sclk - 1)) / pl->sclk) > rdev->pm.dpm.dyn_state.mclk_sclk_ratio) in btc_adjust_clock_combinations()
1290 (rdev->pm.dpm.dyn_state.mclk_sclk_ratio - 1)) / in btc_adjust_clock_combinations()
1291 rdev->pm.dpm.dyn_state.mclk_sclk_ratio); in btc_adjust_clock_combinations()
1293 if ((pl->sclk - pl->mclk) > rdev->pm.dpm.dyn_state.sclk_mclk_delta) in btc_adjust_clock_combinations()
1297 rdev->pm.dpm.dyn_state.sclk_mclk_delta); in btc_adjust_clock_combinations()
1324 if ((*vddc - *vddci) > rdev->pm.dpm.dyn_state.vddc_vddci_delta) { in btc_apply_voltage_delta_rules()
1326 (*vddc - rdev->pm.dpm.dyn_state.vddc_vddci_delta)); in btc_apply_voltage_delta_rules()
1330 if ((*vddci - *vddc) > rdev->pm.dpm.dyn_state.vddc_vddci_delta) { in btc_apply_voltage_delta_rules()
[all …]
H A Dradeon_ci_dpm.c287 if (rdev->pm.dpm.dyn_state.cac_leakage_table.entries == NULL) in ci_populate_bapm_vddc_vid_sidd()
289 if (rdev->pm.dpm.dyn_state.cac_leakage_table.count > 8) in ci_populate_bapm_vddc_vid_sidd()
291 if (rdev->pm.dpm.dyn_state.cac_leakage_table.count != in ci_populate_bapm_vddc_vid_sidd()
292 rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count) in ci_populate_bapm_vddc_vid_sidd()
295 for (i = 0; i < rdev->pm.dpm.dyn_state.cac_leakage_table.count; i++) { in ci_populate_bapm_vddc_vid_sidd()
297 lo_vid[i] = ci_convert_to_vid(rdev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc1); in ci_populate_bapm_vddc_vid_sidd()
298 hi_vid[i] = ci_convert_to_vid(rdev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc2); in ci_populate_bapm_vddc_vid_sidd()
299 hi2_vid[i] = ci_convert_to_vid(rdev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc3); in ci_populate_bapm_vddc_vid_sidd()
301 lo_vid[i] = ci_convert_to_vid(rdev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc); in ci_populate_bapm_vddc_vid_sidd()
302 hi_vid[i] = ci_convert_to_vid((u16)rdev->pm.dpm.dyn_state.cac_leakage_table.entries[i].leakage); in ci_populate_bapm_vddc_vid_sidd()
[all …]
H A Dradeon_si_dpm.c2170 struct radeon_ppm_table *ppm = rdev->pm.dpm.dyn_state.ppm_table; in si_populate_smc_tdp_limits()
2543 &rdev->pm.dpm.dyn_state.cac_leakage_table; in si_get_cac_std_voltage_max_min()
2946 &rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table; in si_get_vce_clock_voltage()
3031 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac; in si_apply_state_adjust_rules()
3033 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc; in si_apply_state_adjust_rules()
3053 btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk, in si_apply_state_adjust_rules()
3055 btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk, in si_apply_state_adjust_rules()
3057 btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk, in si_apply_state_adjust_rules()
3159 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk, in si_apply_state_adjust_rules()
3162 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk, in si_apply_state_adjust_rules()
[all …]
H A Dradeon_ni_dpm.c808 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac; in ni_apply_state_adjust_rules()
810 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc; in ni_apply_state_adjust_rules()
879 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk, in ni_apply_state_adjust_rules()
882 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk, in ni_apply_state_adjust_rules()
885 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk, in ni_apply_state_adjust_rules()
888 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk, in ni_apply_state_adjust_rules()
902 if (ps->performance_levels[i].vddc > rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.vddc) in ni_apply_state_adjust_rules()
905 if (ps->performance_levels[i].vddc < rdev->pm.dpm.dyn_state.min_vddc_for_pcie_gen2) in ni_apply_state_adjust_rules()
1018 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk); in ni_patch_dependency_tables_based_on_leakage()
1021 &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk); in ni_patch_dependency_tables_based_on_leakage()
[all …]
H A Dradeon_kv_dpm.c562 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk; in kv_convert_vid2_to_vid7()
584 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk; in kv_convert_vid7_to_vid2()
725 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk; in kv_program_bootup_state()
827 &rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table; in kv_populate_uvd_table()
900 &rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table; in kv_populate_vce_table()
961 &rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table; in kv_populate_samu_table()
1027 &rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table; in kv_populate_acp_table()
1086 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk; in kv_calculate_dfs_bypass_settings()
1433 &rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table; in kv_update_uvd_dpm()
1469 &rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table; in kv_get_vce_boot_level()
[all …]
H A Dradeon_rv770_dpm.c2264 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk = pl->sclk; in rv7xx_parse_pplib_clock_info()
2265 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.mclk = pl->mclk; in rv7xx_parse_pplib_clock_info()
2266 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddc = pl->vddc; in rv7xx_parse_pplib_clock_info()
2267 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddci = pl->vddci; in rv7xx_parse_pplib_clock_info()
/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/powerplay/hwmgr/
H A Damdgpu_processpptables.c1218 hwmgr->dyn_state.vddc_dependency_on_sclk = NULL; in init_clock_voltage_dependency()
1219 hwmgr->dyn_state.vddci_dependency_on_mclk = NULL; in init_clock_voltage_dependency()
1220 hwmgr->dyn_state.vddc_dependency_on_mclk = NULL; in init_clock_voltage_dependency()
1221 hwmgr->dyn_state.vddc_dep_on_dal_pwrl = NULL; in init_clock_voltage_dependency()
1222 hwmgr->dyn_state.mvdd_dependency_on_mclk = NULL; in init_clock_voltage_dependency()
1223 hwmgr->dyn_state.vce_clock_voltage_dependency_table = NULL; in init_clock_voltage_dependency()
1224 hwmgr->dyn_state.uvd_clock_voltage_dependency_table = NULL; in init_clock_voltage_dependency()
1225 hwmgr->dyn_state.samu_clock_voltage_dependency_table = NULL; in init_clock_voltage_dependency()
1226 hwmgr->dyn_state.acp_clock_voltage_dependency_table = NULL; in init_clock_voltage_dependency()
1227 hwmgr->dyn_state.ppm_parameter_table = NULL; in init_clock_voltage_dependency()
[all …]
H A Damdgpu_smu8_hwmgr.c80 hwmgr->dyn_state.vce_clock_voltage_dependency_table; in smu8_get_eclk_level()
111 hwmgr->dyn_state.vddc_dependency_on_sclk; in smu8_get_sclk_level()
141 hwmgr->dyn_state.uvd_clock_voltage_dependency_table; in smu8_get_uvd_level()
267 hwmgr->dyn_state.vddc_dependency_on_sclk; in smu8_construct_max_power_limits_table()
309 hwmgr->dyn_state.vddc_dep_on_dal_pwrl = table_clk_vlt; in smu8_init_dynamic_state_adjustment_rule_settings()
410 &hwmgr->dyn_state.max_clock_voltage_on_ac); in smu8_get_system_info_data()
449 hwmgr->dyn_state.vddc_dependency_on_sclk; in smu8_upload_pptable_to_smu()
451 hwmgr->dyn_state.vdd_gfx_dependency_on_sclk; in smu8_upload_pptable_to_smu()
453 hwmgr->dyn_state.acp_clock_voltage_dependency_table; in smu8_upload_pptable_to_smu()
455 hwmgr->dyn_state.uvd_clock_voltage_dependency_table; in smu8_upload_pptable_to_smu()
[all …]
H A Damdgpu_smu7_hwmgr.c280 hwmgr->dyn_state.mvdd_dependency_on_mclk); in smu7_construct_voltage_tables()
300 hwmgr->dyn_state.vddci_dependency_on_mclk); in smu7_construct_voltage_tables()
325 hwmgr->dyn_state.vddc_dependency_on_mclk); in smu7_construct_voltage_tables()
681 hwmgr->dyn_state.vddc_dependency_on_sclk; in smu7_setup_dpm_tables_v0()
683 hwmgr->dyn_state.vddc_dependency_on_mclk; in smu7_setup_dpm_tables_v0()
685 hwmgr->dyn_state.cac_leakage_table; in smu7_setup_dpm_tables_v0()
735 allowed_vdd_mclk_table = hwmgr->dyn_state.vddci_dependency_on_mclk; in smu7_setup_dpm_tables_v0()
746 allowed_vdd_mclk_table = hwmgr->dyn_state.mvdd_dependency_on_mclk; in smu7_setup_dpm_tables_v0()
1846 hwmgr->dyn_state.max_clock_voltage_on_dc.vddc = in smu7_patch_clock_voltage_limits_with_vddc_leakage()
2110 hwmgr->dyn_state.max_clock_voltage_on_ac.sclk = table_info->max_clock_voltage_on_ac.sclk; in smu7_set_private_data_based_on_pptable_v1()
[all …]
H A Damdgpu_hwmgr.c255 if ((hwmgr->dyn_state.max_clock_voltage_on_dc.sclk == 0) || in hwmgr_hw_init()
256 (hwmgr->dyn_state.max_clock_voltage_on_dc.mclk == 0)) in hwmgr_hw_init()
257 hwmgr->dyn_state.max_clock_voltage_on_dc = in hwmgr_hw_init()
258 hwmgr->dyn_state.max_clock_voltage_on_ac; in hwmgr_hw_init()
H A Damdgpu_process_pptables_v1_0.c607 hwmgr->dyn_state.cac_dtp_table = kzalloc(table_size, GFP_KERNEL); in get_cac_tdp_table()
609 if (NULL == hwmgr->dyn_state.cac_dtp_table) { in get_cac_tdp_table()
829 hwmgr->dyn_state.max_clock_voltage_on_dc.sclk = in init_clock_voltage_dependency()
831 hwmgr->dyn_state.max_clock_voltage_on_dc.mclk = in init_clock_voltage_dependency()
833 hwmgr->dyn_state.max_clock_voltage_on_dc.vddc = in init_clock_voltage_dependency()
835 hwmgr->dyn_state.max_clock_voltage_on_dc.vddci = in init_clock_voltage_dependency()
1143 kfree(hwmgr->dyn_state.cac_dtp_table); in pp_tables_v1_0_uninitialize()
1144 hwmgr->dyn_state.cac_dtp_table = NULL; in pp_tables_v1_0_uninitialize()
H A Damdgpu_vega10_processpptables.c1028 hwmgr->dyn_state.max_clock_voltage_on_dc.sclk = in init_powerplay_extended_tables()
1030 hwmgr->dyn_state.max_clock_voltage_on_dc.mclk = in init_powerplay_extended_tables()
1032 hwmgr->dyn_state.max_clock_voltage_on_dc.vddc = in init_powerplay_extended_tables()
1034 hwmgr->dyn_state.max_clock_voltage_on_dc.vddci = in init_powerplay_extended_tables()
1271 kfree(hwmgr->dyn_state.cac_dtp_table); in vega10_pp_tables_uninitialize()
1272 hwmgr->dyn_state.cac_dtp_table = NULL; in vega10_pp_tables_uninitialize()
H A Damdgpu_smu10_hwmgr.c172 hwmgr->dyn_state.vddc_dep_on_dal_pwrl = table_clk_vlt; in smu10_init_dynamic_state_adjustment_rule_settings()
188 &hwmgr->dyn_state.max_clock_voltage_on_ac); in smu10_get_system_info_data()
565 kfree(hwmgr->dyn_state.vddc_dep_on_dal_pwrl); in smu10_hwmgr_backend_fini()
566 hwmgr->dyn_state.vddc_dep_on_dal_pwrl = NULL; in smu10_hwmgr_backend_fini()
H A Damdgpu_ppatomctrl.c1135 for (entry_id = 0; entry_id < hwmgr->dyn_state.vddc_dependency_on_sclk->count; entry_id++) { in atomctrl_get_voltage_evv()
1136 if (hwmgr->dyn_state.vddc_dependency_on_sclk->entries[entry_id].v == virtual_voltage_id) { in atomctrl_get_voltage_evv()
1142 if (entry_id >= hwmgr->dyn_state.vddc_dependency_on_sclk->count) { in atomctrl_get_voltage_evv()
1151 cpu_to_le32(hwmgr->dyn_state.vddc_dependency_on_sclk->entries[entry_id].clk); in atomctrl_get_voltage_evv()
H A Damdgpu_vega10_hwmgr.c801 hwmgr->dyn_state.max_clock_voltage_on_ac.sclk = in vega10_set_private_data_based_on_pptable()
803 hwmgr->dyn_state.max_clock_voltage_on_ac.mclk = in vega10_set_private_data_based_on_pptable()
805 hwmgr->dyn_state.max_clock_voltage_on_ac.vddc = in vega10_set_private_data_based_on_pptable()
807 hwmgr->dyn_state.max_clock_voltage_on_ac.vddci = in vega10_set_private_data_based_on_pptable()
815 kfree(hwmgr->dyn_state.vddc_dep_on_dal_pwrl); in vega10_hwmgr_backend_fini()
816 hwmgr->dyn_state.vddc_dep_on_dal_pwrl = NULL; in vega10_hwmgr_backend_fini()
3200 &(hwmgr->dyn_state.max_clock_voltage_on_ac) : in vega10_apply_state_adjust_rules()
3201 &(hwmgr->dyn_state.max_clock_voltage_on_dc); in vega10_apply_state_adjust_rules()
3230 max_limits = &(hwmgr->dyn_state.max_clock_voltage_on_ac); in vega10_apply_state_adjust_rules()
H A Damdgpu_smu7_powertune.c1127 cac_table = hwmgr->dyn_state.cac_dtp_table; in smu7_enable_power_containment()
1212 cac_table = hwmgr->dyn_state.cac_dtp_table; in smu7_power_control_set_level()
H A Damdgpu_smu_helper.c522 hwmgr->dyn_state.vddc_dep_on_dal_pwrl = table_clk_vlt; in phm_initializa_dynamic_state_adjustment_rule_settings()
/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/powerplay/smumgr/
H A Damdgpu_ci_smumgr.c422 hwmgr->dyn_state.vddc_dependency_on_sclk, clock, in ci_populate_single_graphic_level()
434 hwmgr->dyn_state.vddc_phase_shed_limits_table, in ci_populate_single_graphic_level()
535 tdc_limit = (uint16_t)(hwmgr->dyn_state.cac_dtp_table->usTDC * 256); in ci_populate_tdc_limit()
588 PP_ASSERT_WITH_CODE(NULL != hwmgr->dyn_state.cac_leakage_table, in ci_populate_bapm_vddc_vid_sidd()
590 PP_ASSERT_WITH_CODE(hwmgr->dyn_state.cac_leakage_table->count <= 8, in ci_populate_bapm_vddc_vid_sidd()
592 …PP_ASSERT_WITH_CODE(hwmgr->dyn_state.cac_leakage_table->count == hwmgr->dyn_state.vddc_dependency_… in ci_populate_bapm_vddc_vid_sidd()
595 for (i = 0; (uint32_t) i < hwmgr->dyn_state.cac_leakage_table->count; i++) { in ci_populate_bapm_vddc_vid_sidd()
597 lo_vid[i] = convert_to_vid(hwmgr->dyn_state.cac_leakage_table->entries[i].Vddc1); in ci_populate_bapm_vddc_vid_sidd()
598 hi_vid[i] = convert_to_vid(hwmgr->dyn_state.cac_leakage_table->entries[i].Vddc2); in ci_populate_bapm_vddc_vid_sidd()
599 hi2_vid[i] = convert_to_vid(hwmgr->dyn_state.cac_leakage_table->entries[i].Vddc3); in ci_populate_bapm_vddc_vid_sidd()
[all …]
H A Damdgpu_iceland_smumgr.c330 tdc_limit = (uint16_t)(hwmgr->dyn_state.cac_dtp_table->usTDC * 256); in iceland_populate_tdc_limit()
381 struct phm_cac_tdp_table *cac_table = hwmgr->dyn_state.cac_dtp_table; in iceland_populate_bapm_vddc_base_leakage_sidd()
401 PP_ASSERT_WITH_CODE(NULL != hwmgr->dyn_state.cac_leakage_table, in iceland_populate_bapm_vddc_vid_sidd()
403 PP_ASSERT_WITH_CODE(hwmgr->dyn_state.cac_leakage_table->count <= 8, in iceland_populate_bapm_vddc_vid_sidd()
405 …PP_ASSERT_WITH_CODE(hwmgr->dyn_state.cac_leakage_table->count == hwmgr->dyn_state.vddc_dependency_… in iceland_populate_bapm_vddc_vid_sidd()
409 for (i = 0; (uint32_t) i < hwmgr->dyn_state.cac_leakage_table->count; i++) { in iceland_populate_bapm_vddc_vid_sidd()
410 lo_vid[i] = convert_to_vid(hwmgr->dyn_state.cac_leakage_table->entries[i].Vddc1); in iceland_populate_bapm_vddc_vid_sidd()
411 hi_vid[i] = convert_to_vid(hwmgr->dyn_state.cac_leakage_table->entries[i].Vddc2); in iceland_populate_bapm_vddc_vid_sidd()
545 PP_ASSERT_WITH_CODE(NULL != hwmgr->dyn_state.vddc_dependency_on_sclk, in iceland_get_std_voltage_value_sidd()
549 if (NULL == hwmgr->dyn_state.cac_leakage_table) { in iceland_get_std_voltage_value_sidd()
[all …]

12