| /netbsd-src/sys/external/bsd/drm2/dist/drm/radeon/ |
| H A D | radeon_kv_dpm.c | 471 pi->dpm_table_start = tmp; in kv_process_firmware_header()
491 pi->dpm_table_start + in kv_enable_dpm_voltage_scaling()
507 pi->dpm_table_start + in kv_set_dpm_interval()
521 pi->dpm_table_start + in kv_set_dpm_boot_state()
712 pi->dpm_table_start + in kv_update_sclk_t()
761 pi->dpm_table_start + in kv_enable_auto_thermal_throttling()
775 pi->dpm_table_start + in kv_upload_dpm_settings()
785 pi->dpm_table_start + in kv_upload_dpm_settings()
866 pi->dpm_table_start + in kv_populate_uvd_table()
876 pi->dpm_table_start + in kv_populate_uvd_table()
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| H A D | kv_dpm.h | 124 u32 dpm_table_start; member
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| H A D | ci_dpm.h | 220 u32 dpm_table_start; member
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| H A D | radeon_ci_dpm.c | 1332 pi->dpm_table_start + in ci_update_sclk_t()
1835 pi->dpm_table_start = tmp; in ci_process_firmware_header()
3286 u32 level_array_address = pi->dpm_table_start + in ci_populate_all_graphic_levels()
3333 u32 level_array_address = pi->dpm_table_start + in ci_populate_all_memory_levels()
3698 pi->dpm_table_start + in ci_init_smc_table()
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| /netbsd-src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/ |
| H A D | amdgpu_kv_dpm.c | 598 pi->dpm_table_start = tmp; in kv_process_firmware_header()
618 pi->dpm_table_start + in kv_enable_dpm_voltage_scaling()
634 pi->dpm_table_start + in kv_set_dpm_interval()
648 pi->dpm_table_start + in kv_set_dpm_boot_state()
795 pi->dpm_table_start + in kv_update_sclk_t()
844 pi->dpm_table_start + in kv_enable_auto_thermal_throttling()
858 pi->dpm_table_start + in kv_upload_dpm_settings()
868 pi->dpm_table_start + in kv_upload_dpm_settings()
949 pi->dpm_table_start + in kv_populate_uvd_table()
959 pi->dpm_table_start + in kv_populate_uvd_table()
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| H A D | kv_dpm.h | 150 u32 dpm_table_start; member
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| /netbsd-src/sys/external/bsd/drm2/dist/drm/amd/powerplay/smumgr/ |
| H A D | amdgpu_polaris10_smumgr.c | 127 uint32_t dpm_table_start; in polaris10_setup_graphics_level_structure() local
137 &dpm_table_start, 0x40000), in polaris10_setup_graphics_level_structure()
144 vr_config_address = dpm_table_start + offsetof(SMU74_Discrete_DpmTable, VRConfig); in polaris10_setup_graphics_level_structure()
151 graphics_level_address = dpm_table_start + offsetof(SMU74_Discrete_DpmTable, GraphicsLevel); in polaris10_setup_graphics_level_structure()
159 graphics_level_address = dpm_table_start + offsetof(SMU74_Discrete_DpmTable, MemoryLevel); in polaris10_setup_graphics_level_structure()
168 graphics_level_address = dpm_table_start + offsetof(SMU74_Discrete_DpmTable, BootMVdd); in polaris10_setup_graphics_level_structure()
992 uint32_t array = smu_data->smu7_data.dpm_table_start + in polaris10_populate_all_graphic_levels()
1136 uint32_t array = smu_data->smu7_data.dpm_table_start + in polaris10_populate_all_memory_levels()
2019 smu_data->smu7_data.dpm_table_start + in polaris10_init_smc_table()
2193 mm_boot_level_offset = smu_data->smu7_data.dpm_table_start + offsetof(SMU74_Discrete_DpmTable, in polaris10_update_uvd_smc_table()
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| H A D | ci_smumgr.h | 65 uint32_t dpm_table_start; member
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| H A D | smu7_smumgr.h | 47 uint32_t dpm_table_start; member
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| H A D | amdgpu_fiji_smumgr.c | 1017 uint32_t array = smu_data->smu7_data.dpm_table_start + in fiji_populate_all_graphic_levels()
1233 uint32_t array = smu_data->smu7_data.dpm_table_start + in fiji_populate_all_memory_levels()
2112 smu_data->smu7_data.dpm_table_start + in fiji_init_smc_table()
2284 smu_data->smu7_data.dpm_table_start + in fiji_update_sclk_threshold()
2381 mm_boot_level_offset = smu_data->smu7_data.dpm_table_start + offsetof(SMU73_Discrete_DpmTable, in fiji_update_uvd_smc_table()
2416 mm_boot_level_offset = smu_data->smu7_data.dpm_table_start + in fiji_update_vce_smc_table()
2463 smu_data->smu7_data.dpm_table_start = tmp; in fiji_process_firmware_header()
2560 uint32_t array = smu_data->smu7_data.dpm_table_start + in fiji_update_dpm_settings()
2563 uint32_t mclk_array = smu_data->smu7_data.dpm_table_start + in fiji_update_dpm_settings()
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| H A D | amdgpu_vegam_smumgr.c | 244 smu_data->smu7_data.dpm_table_start = tmp; in vegam_process_firmware_header()
347 mm_boot_level_offset = smu_data->smu7_data.dpm_table_start + offsetof(SMU75_Discrete_DpmTable, in vegam_update_uvd_smc_table()
382 mm_boot_level_offset = smu_data->smu7_data.dpm_table_start + in vegam_update_vce_smc_table()
876 uint32_t array = smu_data->smu7_data.dpm_table_start + in vegam_populate_all_graphic_levels()
1043 uint32_t array = smu_data->smu7_data.dpm_table_start + in vegam_populate_all_memory_levels()
2136 smu_data->smu7_data.dpm_table_start + in vegam_init_smc_table()
2232 smu_data->smu7_data.dpm_table_start + in vegam_update_sclk_threshold()
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| H A D | amdgpu_tonga_smumgr.c | 699 uint32_t level_array_address = smu_data->smu7_data.dpm_table_start + in tonga_populate_all_graphic_levels()
1101 smu_data->smu7_data.dpm_table_start + in tonga_populate_all_memory_levels()
2442 smu_data->smu7_data.dpm_table_start + offsetof(SMU72_Discrete_DpmTable, SystemFlags), in tonga_init_smc_table()
2587 smu_data->smu7_data.dpm_table_start + in tonga_update_sclk_threshold()
2692 mm_boot_level_offset = smu_data->smu7_data.dpm_table_start + in tonga_update_uvd_smc_table()
2726 mm_boot_level_offset = smu_data->smu7_data.dpm_table_start + in tonga_update_vce_smc_table()
2775 smu_data->smu7_data.dpm_table_start = tmp; in tonga_process_firmware_header()
3159 uint32_t array = smu_data->smu7_data.dpm_table_start + in tonga_update_dpm_settings()
3162 uint32_t mclk_array = smu_data->smu7_data.dpm_table_start + in tonga_update_dpm_settings()
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| H A D | amdgpu_ci_smumgr.c | 481 uint32_t array = smu_data->dpm_table_start + in ci_populate_all_graphic_levels()
1312 …uint32_t level_array_address = smu_data->dpm_table_start + offsetof(SMU7_Discrete_DpmTable, Memory… in ci_populate_all_memory_levels()
2106 result = ci_copy_bytes_to_smc(hwmgr, smu_data->dpm_table_start + in ci_init_smc_table()
2232 smu_data->dpm_table_start + in ci_update_sclk_threshold()
2388 ci_data->dpm_table_start = tmp; in ci_process_firmware_header()
2771 uint32_t array = smu_data->dpm_table_start + in ci_update_dpm_settings()
2774 uint32_t mclk_array = smu_data->dpm_table_start + in ci_update_dpm_settings()
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| H A D | amdgpu_iceland_smumgr.c | 969 uint32_t level_array_adress = smu_data->smu7_data.dpm_table_start + in iceland_populate_all_graphic_levels()
1359 …uint32_t level_array_adress = smu_data->smu7_data.dpm_table_start + offsetof(SMU71_Discrete_DpmTab… in iceland_populate_all_memory_levels()
2062 result = smu7_copy_bytes_to_smc(hwmgr, smu_data->smu7_data.dpm_table_start + in iceland_init_smc_table()
2197 smu_data->smu7_data.dpm_table_start + in iceland_update_sclk_threshold()
2297 smu7_data->dpm_table_start = tmp; in iceland_process_firmware_header()
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| /netbsd-src/sys/external/bsd/drm2/dist/drm/amd/powerplay/hwmgr/ |
| H A D | smu10_hwmgr.h | 246 uint32_t dpm_table_start; member
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| H A D | smu8_hwmgr.h | 260 uint32_t dpm_table_start; member
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