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Searched refs:dpcd (Results 1 – 24 of 24) sorted by relevance

/netbsd-src/sys/external/bsd/drm2/dist/drm/nouveau/
H A Dnouveau_dp.c45 nouveau_dp_probe_oui(struct drm_device *dev, struct nvkm_i2c_aux *aux, u8 *dpcd) in nouveau_dp_probe_oui() argument
50 if (!(dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT)) in nouveau_dp_probe_oui()
69 u8 dpcd[8]; in nouveau_dp_detect() local
76 ret = nvkm_rdaux(aux, DP_DPCD_REV, dpcd, sizeof(dpcd)); in nouveau_dp_detect()
80 nv_encoder->dp.link_bw = 27000 * dpcd[1]; in nouveau_dp_detect()
81 nv_encoder->dp.link_nr = dpcd[2] & DP_MAX_LANE_COUNT_MASK; in nouveau_dp_detect()
84 nv_encoder->dp.link_nr, nv_encoder->dp.link_bw, dpcd[0]); in nouveau_dp_detect()
97 nouveau_dp_probe_oui(dev, aux, dpcd); in nouveau_dp_detect()
99 ret = nv50_mstm_detect(nv_encoder->dp.mstm, dpcd, nouveau_mst); in nouveau_dp_detect()
H A Dnouveau_encoder.h109 int nv50_mstm_detect(struct nv50_mstm *, u8 dpcd[8], int allow);
/netbsd-src/sys/external/bsd/drm2/dist/include/drm/
H A Ddrm_dp_helper.h1149 void drm_dp_link_train_clock_recovery_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE]);
1150 void drm_dp_link_train_channel_eq_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE]);
1218 drm_dp_max_link_rate(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) in drm_dp_max_link_rate()
1220 return drm_dp_bw_code_to_link_rate(dpcd[DP_MAX_LINK_RATE]); in drm_dp_max_link_rate()
1224 drm_dp_max_lane_count(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) in drm_dp_max_lane_count()
1226 return dpcd[DP_MAX_LANE_COUNT] & DP_MAX_LANE_COUNT_MASK; in drm_dp_max_lane_count()
1230 drm_dp_enhanced_frame_cap(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) in drm_dp_enhanced_frame_cap()
1232 return dpcd[DP_DPCD_REV] >= 0x11 && in drm_dp_enhanced_frame_cap()
1233 (dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP); in drm_dp_enhanced_frame_cap()
1237 drm_dp_fast_training_cap(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) in drm_dp_fast_training_cap()
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H A Ddrm_dp_mst_helper.h607 u8 dpcd[DP_RECEIVER_CAP_SIZE]; member
/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
H A Damdgpu_atombios_dp.c261 const u8 dpcd[DP_DPCD_SIZE], in amdgpu_atombios_dp_get_dp_link_config()
268 unsigned max_link_rate = drm_dp_max_link_rate(dpcd); in amdgpu_atombios_dp_get_dp_link_config()
269 unsigned max_lane_num = drm_dp_max_lane_count(dpcd); in amdgpu_atombios_dp_get_dp_link_config()
330 if (!(dig_connector->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT)) in amdgpu_atombios_dp_probe_oui()
351 memcpy(dig_connector->dpcd, msg, DP_DPCD_SIZE); in amdgpu_atombios_dp_get_dpcd()
353 DRM_DEBUG_KMS("DPCD: %*ph\n", (int)sizeof(dig_connector->dpcd), in amdgpu_atombios_dp_get_dpcd()
354 dig_connector->dpcd); in amdgpu_atombios_dp_get_dpcd()
361 dig_connector->dpcd[0] = 0; in amdgpu_atombios_dp_get_dpcd()
413 ret = amdgpu_atombios_dp_get_dp_link_config(connector, dig_connector->dpcd, in amdgpu_atombios_dp_set_link_config()
436 ret = amdgpu_atombios_dp_get_dp_link_config(connector, dig_connector->dpcd, in amdgpu_atombios_dp_mode_valid_helper()
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H A Damdgpu_mode.h473 u8 dpcd[DP_RECEIVER_CAP_SIZE]; member
/netbsd-src/sys/external/bsd/drm2/dist/drm/radeon/
H A Dradeon_atombios_dp.c319 const u8 dpcd[DP_DPCD_SIZE], in radeon_dp_get_dp_link_config()
325 unsigned max_link_rate = drm_dp_max_link_rate(dpcd); in radeon_dp_get_dp_link_config()
326 unsigned max_lane_num = drm_dp_max_lane_count(dpcd); in radeon_dp_get_dp_link_config()
387 if (!(dig_connector->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT)) in radeon_dp_probe_oui()
408 memcpy(dig_connector->dpcd, msg, DP_DPCD_SIZE); in radeon_dp_getdpcd()
410 DRM_DEBUG_KMS("DPCD: %*ph\n", (int)sizeof(dig_connector->dpcd), in radeon_dp_getdpcd()
411 dig_connector->dpcd); in radeon_dp_getdpcd()
418 dig_connector->dpcd[0] = 0; in radeon_dp_getdpcd()
475 ret = radeon_dp_get_dp_link_config(connector, dig_connector->dpcd, in radeon_dp_set_link_config()
502 ret = radeon_dp_get_dp_link_config(connector, dig_connector->dpcd, in radeon_dp_mode_valid_helper()
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H A Dradeon_dp_mst.c536 dig_connector->dp_lane_count = drm_dp_max_lane_count(dig_connector->dpcd); in radeon_mst_mode_fixup()
537 dig_connector->dp_clock = drm_dp_max_link_rate(dig_connector->dpcd); in radeon_mst_mode_fixup()
687 if (dig_connector->dpcd[DP_DPCD_REV] < 0x12) in radeon_dp_mst_probe()
H A Dradeon_mode.h491 u8 dpcd[DP_RECEIVER_CAP_SIZE]; member
/netbsd-src/sys/external/bsd/drm2/dist/drm/i915/display/
H A Dintel_dp_link_training.c158 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) in intel_dp_link_training_clock_recovery()
189 if (intel_dp->dpcd[DP_DPCD_REV] >= DP_DPCD_REV_14) in intel_dp_link_training_clock_recovery()
198 drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd); in intel_dp_link_training_clock_recovery()
259 sink_tps4 = drm_dp_tps4_supported(intel_dp->dpcd); in intel_dp_training_pattern()
274 sink_tps3 = drm_dp_tps3_supported(intel_dp->dpcd); in intel_dp_training_pattern()
309 drm_dp_link_train_channel_eq_delay(intel_dp->dpcd); in intel_dp_link_training_channel_equalization()
H A Dintel_dp.c177 max_rate = drm_dp_bw_code_to_link_rate(intel_dp->dpcd[DP_MAX_LINK_RATE]); in intel_dp_set_sink_rates()
221 int sink_max = drm_dp_max_lane_count(intel_dp->dpcd); in intel_dp_max_common_lane_count()
265 ds_max_dotclk = drm_dp_downstream_max_clock(intel_dp->dpcd, in intel_dp_downstream_max_dotclock()
1939 bpc = drm_dp_downstream_max_bpc(intel_dp->dpcd, intel_dp->downstream_ports); in intel_dp_compute_bpp()
2560 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) in intel_dp_prepare()
2570 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) in intel_dp_prepare()
2585 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) in intel_dp_prepare()
3178 return intel_dp->dpcd[DP_DPCD_REV] == 0x11 && in downstream_hpd_needs_d0()
3179 intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT && in downstream_hpd_needs_d0()
3205 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11) in intel_dp_sink_dpms()
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H A Dintel_lspcon.c84 if (drm_dp_read_desc(&dp->aux, &dp->desc, drm_dp_is_branch(dp->dpcd))) { in lspcon_detect_vendor()
H A Dintel_display_types.h1234 u8 dpcd[DP_RECEIVER_CAP_SIZE]; member
H A Dintel_psr.c456 drm_dp_tps3_supported(intel_dp->dpcd)) in intel_psr1_get_tp_time()
H A Dintel_ddi.c4230 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) in intel_ddi_prepare_link_retrain()
/netbsd-src/sys/external/bsd/drm2/dist/drm/i915/gvt/
H A Ddisplay.c320 kfree(port->dpcd); in clean_virtual_dp_monitor()
321 port->dpcd = NULL; in clean_virtual_dp_monitor()
336 port->dpcd = kzalloc(sizeof(*(port->dpcd)), GFP_KERNEL); in setup_virtual_dp_monitor()
337 if (!port->dpcd) { in setup_virtual_dp_monitor()
346 memcpy(port->dpcd->data, dpcd_fix_data, DPCD_HEADER_SIZE); in setup_virtual_dp_monitor()
347 port->dpcd->data_valid = true; in setup_virtual_dp_monitor()
348 port->dpcd->data[DPCD_SINK_COUNT] = 0x1; in setup_virtual_dp_monitor()
H A Dhandlers.c875 static void dp_aux_ch_ctl_link_training(struct intel_vgpu_dpcd_data *dpcd, in dp_aux_ch_ctl_link_training() argument
881 dpcd->data[DPCD_LANE0_1_STATUS] |= DPCD_LANES_CR_DONE; in dp_aux_ch_ctl_link_training()
883 dpcd->data[DPCD_LANE2_3_STATUS] |= DPCD_LANES_CR_DONE; in dp_aux_ch_ctl_link_training()
888 dpcd->data[DPCD_LANE0_1_STATUS] |= DPCD_LANES_EQ_DONE; in dp_aux_ch_ctl_link_training()
889 dpcd->data[DPCD_LANE0_1_STATUS] |= DPCD_SYMBOL_LOCKED; in dp_aux_ch_ctl_link_training()
891 dpcd->data[DPCD_LANE2_3_STATUS] |= DPCD_LANES_EQ_DONE; in dp_aux_ch_ctl_link_training()
892 dpcd->data[DPCD_LANE2_3_STATUS] |= DPCD_SYMBOL_LOCKED; in dp_aux_ch_ctl_link_training()
894 dpcd->data[DPCD_LANE_ALIGN_STATUS_UPDATED] |= in dp_aux_ch_ctl_link_training()
900 dpcd->data[DPCD_SINK_STATUS] = DPCD_SINK_IN_SYNC; in dp_aux_ch_ctl_link_training()
920 struct intel_vgpu_dpcd_data *dpcd = NULL; in dp_aux_ch_ctl_mmio_write() local
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H A Ddisplay.h166 struct intel_vgpu_dpcd_data *dpcd; member
/netbsd-src/sys/external/bsd/drm2/dist/drm/
H A Ddrm_dp_helper.c149 void drm_dp_link_train_clock_recovery_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) in drm_dp_link_train_clock_recovery_delay()
151 unsigned long rd_interval = dpcd[DP_TRAINING_AUX_RD_INTERVAL] & in drm_dp_link_train_clock_recovery_delay()
158 if (rd_interval == 0 || dpcd[DP_DPCD_REV] >= DP_DPCD_REV_14) in drm_dp_link_train_clock_recovery_delay()
167 void drm_dp_link_train_channel_eq_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) in drm_dp_link_train_channel_eq_delay()
169 unsigned long rd_interval = dpcd[DP_TRAINING_AUX_RD_INTERVAL] & in drm_dp_link_train_channel_eq_delay()
389 int drm_dp_downstream_max_clock(const u8 dpcd[DP_RECEIVER_CAP_SIZE], in drm_dp_downstream_max_clock()
393 bool detailed_cap_info = dpcd[DP_DOWNSTREAMPORT_PRESENT] & in drm_dp_downstream_max_clock()
420 int drm_dp_downstream_max_bpc(const u8 dpcd[DP_RECEIVER_CAP_SIZE], in drm_dp_downstream_max_bpc()
424 bool detailed_cap_info = dpcd[DP_DOWNSTREAMPORT_PRESENT] & in drm_dp_downstream_max_bpc()
478 const u8 dpcd[DP_RECEIVER_CAP_SIZE], in drm_dp_downstream_debug()
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H A Ddrm_dp_mst_topology.c3523 ret = drm_dp_dpcd_read(mgr->aux, DP_DPCD_REV, mgr->dpcd, DP_RECEIVER_CAP_SIZE); in drm_dp_mst_topology_mgr_set_mst()
3529 mgr->pbn_div = drm_dp_get_vc_payload_bw(mgr->dpcd[1], in drm_dp_mst_topology_mgr_set_mst()
3530 mgr->dpcd[2] & DP_MAX_LANE_COUNT_MASK); in drm_dp_mst_topology_mgr_set_mst()
3670 ret = drm_dp_dpcd_read(mgr->aux, DP_DPCD_REV, mgr->dpcd, in drm_dp_mst_topology_mgr_resume()
5476 port->mgr->dpcd[DP_DPCD_REV] >= DP_DPCD_REV_14 && in drm_dp_mst_dsc_aux_for_port()
/netbsd-src/sys/external/bsd/drm2/dist/drm/nouveau/nvkm/engine/disp/
H A Dnouveau_nvkm_engine_disp_dp.c58 if (dp->dpcd[DPCD_RC0E_AUX_RD_INTERVAL]) in nvkm_dp_train_sense()
59 mdelay(dp->dpcd[DPCD_RC0E_AUX_RD_INTERVAL] * 4); in nvkm_dp_train_sense()
167 if (lt->dp->dpcd[DPCD_RC02] & DPCD_RC02_TPS3_SUPPORTED) in nvkm_dp_train_eq()
245 dp->dpcd[DPCD_RC02] &= ~DPCD_RC02_TPS3_SUPPORTED; in nvkm_dp_train_links()
246 lt.pc2 = dp->dpcd[DPCD_RC02] & DPCD_RC02_TPS3_SUPPORTED; in nvkm_dp_train_links()
312 if (dp->dpcd[DPCD_RC03] & DPCD_RC03_MAX_DOWNSPREAD) { in nvkm_dp_train_init()
355 const u8 sink_nr = dp->dpcd[DPCD_RC02] & DPCD_RC02_MAX_LANE_COUNT; in nvkm_dp_train()
356 const u8 sink_bw = dp->dpcd[DPCD_RC01_MAX_LINK_RATE]; in nvkm_dp_train()
413 ior->dp.ef = dp->dpcd[DPCD_RC02] & DPCD_RC02_ENHANCED_FRAME_CAP; in nvkm_dp_train()
527 if (!nvkm_rdaux(aux, DPCD_RC00_DPCD_REV, dp->dpcd, in nvkm_dp_enable()
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H A Ddp.h26 u8 dpcd[16]; member
/netbsd-src/sys/external/bsd/drm2/dist/drm/nouveau/dispnv50/
H A Dnouveau_dispnv50_disp.c1365 nv50_mstm_enable(struct nv50_mstm *mstm, u8 dpcd, int state) in nv50_mstm_enable() argument
1382 if (dpcd >= 0x12) { in nv50_mstm_enable()
1404 nv50_mstm_detect(struct nv50_mstm *mstm, u8 dpcd[8], int allow) in nv50_mstm_detect()
1427 } else if (dpcd[0] >= 0x12) { in nv50_mstm_detect()
1428 ret = drm_dp_dpcd_readb(aux, DP_MSTM_CAP, &dpcd[1]); in nv50_mstm_detect()
1432 if (!(dpcd[1] & DP_MST_CAP)) in nv50_mstm_detect()
1433 dpcd[0] = 0x11; in nv50_mstm_detect()
1443 ret = nv50_mstm_enable(mstm, dpcd[0], new_state); in nv50_mstm_detect()
1451 return nv50_mstm_enable(mstm, dpcd[0], 0); in nv50_mstm_detect()
1501 u8 dpcd; in nv50_mstm_new() local
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/netbsd-src/sys/external/bsd/drm2/dist/drm/i915/
H A Di915_debugfs.c2401 seq_printf(m, "\tDPCD rev: %x\n", intel_dp->dpcd[DP_DPCD_REV]); in intel_dp_info()
2406 drm_dp_downstream_debug(m, intel_dp->dpcd, intel_dp->downstream_ports, in intel_dp_info()