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Searched refs:def_instr_begin (Results 1 – 9 of 9) sorted by relevance

/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
H A DAArch64AdvSIMDScalarPass.cpp210 MRI->def_instr_begin(OrigSrc0); in isProfitableToTransform()
223 MRI->def_instr_begin(OrigSrc1); in isProfitableToTransform()
303 MRI->def_instr_begin(OrigSrc0); in transformInstruction()
322 MRI->def_instr_begin(OrigSrc1); in transformInstruction()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/
H A DLiveRangeShrink.cpp200 MachineInstr &DefInstr = *MRI.def_instr_begin(Reg); in runOnMachineFunction()
H A DMachineRegisterInfo.cpp402 def_instr_iterator I = def_instr_begin(Reg); in getVRegDef()
413 def_instr_iterator I = def_instr_begin(Reg); in getUniqueVRegDef()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/GlobalISel/
H A DInstructionSelect.cpp245 MI = &*MRI.def_instr_begin(VReg); in runOnMachineFunction()
/netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/
H A DMachineRegisterInfo.h397 def_instr_iterator def_instr_begin(Register RegNo) const { in def_instr_begin() function
406 return make_range(def_instr_begin(Reg), def_instr_end()); in def_instructions()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
H A DR600OptimizeVectorRegisters.cpp340 It = MRI->def_instr_begin(Reg), E = MRI->def_instr_end(); in runOnMachineFunction()
H A DSIMachineScheduler.cpp294 UI = MRI->def_instr_begin(Reg), in isDefBetween()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/
H A DInstrEmitter.cpp828 MachineInstr &DefMI = *MRI->def_instr_begin(VReg); in EmitDbgInstrRef()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/X86/
H A DX86InstrInfo.cpp955 for (MachineRegisterInfo::def_instr_iterator I = MRI.def_instr_begin(BaseReg), in regIsPICBase()