Searched refs:cw2 (Results 1 – 8 of 8) sorted by relevance
/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/display/dmub/src/ |
H A D | amdgpu_dmub_dcn20.c | 136 const struct dmub_window *cw2, in dmub_dcn20_setup_windows() argument 147 dmub_dcn20_translate_addr(&cw2->offset, fb_base, fb_offset, &offset); in dmub_dcn20_setup_windows() 151 REG_WRITE(DMCUB_REGION3_CW2_BASE_ADDRESS, cw2->region.base); in dmub_dcn20_setup_windows() 153 DMCUB_REGION3_CW2_TOP_ADDRESS, cw2->region.top, in dmub_dcn20_setup_windows()
|
H A D | amdgpu_dmub_srv.c | 341 struct dmub_window cw0, cw1, cw2, cw3, cw4, cw5, cw6; in dmub_srv_hw_init() local 376 cw2.offset.quad_part = data_fb->gpu_addr; in dmub_srv_hw_init() 377 cw2.region.base = DMUB_CW0_BASE + inst_fb->size; in dmub_srv_hw_init() 378 cw2.region.top = cw2.region.base + data_fb->size; in dmub_srv_hw_init() 402 dmub->hw_funcs.setup_windows(dmub, &cw2, &cw3, &cw4, in dmub_srv_hw_init()
|
H A D | dmub_dcn20.h | 171 const struct dmub_window *cw2,
|
/netbsd-src/sys/dev/qbus/ |
H A D | tsreg.h | 89 unsigned short cw2; /* high order data pointer address (A21-16) */ member
|
H A D | ts.c | 466 sc->sc_vts->cmd.cw2 = HIWORD(sc->sc_dmam->dm_segs[0].ds_addr); in tsstart() 520 sc->sc_vts->cmd.cw2 = HIWORD(&sc->sc_bts->chr); in tswchar()
|
/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/display/dmub/inc/ |
H A D | dmub_srv.h | 247 const struct dmub_window *cw2,
|
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/VE/ |
H A D | VEInstrFormats.td | 155 bits<1> cw2 = 0; 168 let Inst{6} = cw2;
|
H A D | VEInstrInfo.td | 1300 let cw = 0, cw2 = 0 in defm CMOVL : RRCMOVm<"cmov.l.${cfw}", 0x3B, I64, i64>; 1301 let cw = 1, cw2 = 0 in defm CMOVW : RRCMOVm<"cmov.w.${cfw}", 0x3B, I32, i32>; 1302 let cw = 0, cw2 = 1 in defm CMOVD : RRCMOVm<"cmov.d.${cfw}", 0x3B, I64, f64>; 1303 let cw = 1, cw2 = 1 in defm CMOVS : RRCMOVm<"cmov.s.${cfw}", 0x3B, F32, f32>;
|