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Searched refs:createReg (Results 1 – 25 of 77) sorted by relevance

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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Mips/Disassembler/
H A DMipsDisassembler.cpp638 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, in DecodeDAHIDATIMMR6()
640 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, in DecodeDAHIDATIMMR6()
652 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, in DecodeDAHIDATI()
654 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, in DecodeDAHIDATI()
690 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, in DecodeAddiGroupBranch()
693 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, in DecodeAddiGroupBranch()
710 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, in DecodePOP35GroupBranchMMR6()
712 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, in DecodePOP35GroupBranchMMR6()
717 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, in DecodePOP35GroupBranchMMR6()
719 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, in DecodePOP35GroupBranchMMR6()
[all …]
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/Disassembler/
H A DPPCDisassembler.cpp87 Inst.addOperand(MCOperand::createReg(Regs[RegNo])); in decodeRegisterClass()
222 Inst.addOperand(MCOperand::createReg(VSRpRegs[RegNo >> 1])); in decodeVSRpEvenOperands()
245 Inst.addOperand(MCOperand::createReg(RRegsNoR0[Base])); in decodeMemRIOperands()
252 Inst.insert(Inst.begin(), MCOperand::createReg(RRegsNoR0[Base])); in decodeMemRIOperands()
257 Inst.addOperand(MCOperand::createReg(RRegsNoR0[Base])); in decodeMemRIOperands()
273 Inst.addOperand(MCOperand::createReg(RRegsNoR0[Base])); in decodeMemRIXOperands()
275 Inst.insert(Inst.begin(), MCOperand::createReg(RRegsNoR0[Base])); in decodeMemRIXOperands()
278 Inst.addOperand(MCOperand::createReg(RRegsNoR0[Base])); in decodeMemRIXOperands()
295 Inst.addOperand(MCOperand::createReg(RRegs[Base])); in decodeMemRIHashOperands()
310 Inst.addOperand(MCOperand::createReg(RRegsNoR0[Base])); in decodeMemRIX16Operands()
[all …]
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/Disassembler/
H A DRISCVDisassembler.cpp74 Inst.addOperand(MCOperand::createReg(Reg)); in DecodeGPRRegisterClass()
85 Inst.addOperand(MCOperand::createReg(Reg)); in DecodeFPR16RegisterClass()
96 Inst.addOperand(MCOperand::createReg(Reg)); in DecodeFPR32RegisterClass()
107 Inst.addOperand(MCOperand::createReg(Reg)); in DecodeFPR32CRegisterClass()
118 Inst.addOperand(MCOperand::createReg(Reg)); in DecodeFPR64RegisterClass()
129 Inst.addOperand(MCOperand::createReg(Reg)); in DecodeFPR64CRegisterClass()
160 Inst.addOperand(MCOperand::createReg(Reg)); in DecodeGPRCRegisterClass()
171 Inst.addOperand(MCOperand::createReg(Reg)); in DecodeVRRegisterClass()
191 Inst.addOperand(MCOperand::createReg(Reg)); in DecodeVRM2RegisterClass()
211 Inst.addOperand(MCOperand::createReg(Reg)); in DecodeVRM4RegisterClass()
[all …]
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/SystemZ/Disassembler/
H A DSystemZDisassembler.cpp88 Inst.addOperand(MCOperand::createReg(RegNo)); in decodeRegisterClass()
296 Inst.addOperand(MCOperand::createReg(Base == 0 ? 0 : Regs[Base])); in decodeBDAddr12Operand()
306 Inst.addOperand(MCOperand::createReg(Base == 0 ? 0 : Regs[Base])); in decodeBDAddr20Operand()
317 Inst.addOperand(MCOperand::createReg(Base == 0 ? 0 : Regs[Base])); in decodeBDXAddr12Operand()
319 Inst.addOperand(MCOperand::createReg(Index == 0 ? 0 : Regs[Index])); in decodeBDXAddr12Operand()
329 Inst.addOperand(MCOperand::createReg(Base == 0 ? 0 : Regs[Base])); in decodeBDXAddr20Operand()
331 Inst.addOperand(MCOperand::createReg(Index == 0 ? 0 : Regs[Index])); in decodeBDXAddr20Operand()
341 Inst.addOperand(MCOperand::createReg(Base == 0 ? 0 : Regs[Base])); in decodeBDLAddr12Len4Operand()
353 Inst.addOperand(MCOperand::createReg(Base == 0 ? 0 : Regs[Base])); in decodeBDLAddr12Len8Operand()
365 Inst.addOperand(MCOperand::createReg(Base == 0 ? 0 : Regs[Base])); in decodeBDRAddr12Operand()
[all …]
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Mips/MCTargetDesc/
H A DMipsTargetStreamer.cpp173 TmpInst.addOperand(MCOperand::createReg(Reg0)); in emitR()
182 TmpInst.addOperand(MCOperand::createReg(Reg0)); in emitRX()
195 emitRX(Opcode, Reg0, MCOperand::createReg(Reg1), IDLoc, STI); in emitRR()
213 TmpInst.addOperand(MCOperand::createReg(Reg0)); in emitRRX()
214 TmpInst.addOperand(MCOperand::createReg(Reg1)); in emitRRX()
223 emitRRX(Opcode, Reg0, Reg1, MCOperand::createReg(Reg2), IDLoc, STI); in emitRRR()
231 TmpInst.addOperand(MCOperand::createReg(Reg0)); in emitRRRX()
232 TmpInst.addOperand(MCOperand::createReg(Reg1)); in emitRRRX()
233 TmpInst.addOperand(MCOperand::createReg(Reg2)); in emitRRRX()
251 TmpInst.addOperand(MCOperand::createReg(Reg0)); in emitRRIII()
[all …]
H A DMipsNaClELFStreamer.cpp105 MaskInst.addOperand(MCOperand::createReg(AddrReg)); in emitMask()
106 MaskInst.addOperand(MCOperand::createReg(AddrReg)); in emitMask()
107 MaskInst.addOperand(MCOperand::createReg(MaskReg)); in emitMask()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
H A DARMInstrInfo.cpp41 NopInst.addOperand(MCOperand::createReg(0)); in getNop()
44 NopInst.addOperand(MCOperand::createReg(ARM::R0)); in getNop()
45 NopInst.addOperand(MCOperand::createReg(ARM::R0)); in getNop()
47 NopInst.addOperand(MCOperand::createReg(0)); in getNop()
48 NopInst.addOperand(MCOperand::createReg(0)); in getNop()
H A DARMAsmPrinter.cpp1447 TmpInst.addOperand(MCOperand::createReg(MI->getOperand(0).getReg())); in emitInstruction()
1468 TmpInst.addOperand(MCOperand::createReg(0)); in emitInstruction()
1470 TmpInst.addOperand(MCOperand::createReg(0)); in emitInstruction()
1479 TmpInst.addOperand(MCOperand::createReg(MI->getOperand(0).getReg())); in emitInstruction()
1480 TmpInst.addOperand(MCOperand::createReg(MI->getOperand(1).getReg())); in emitInstruction()
1500 TmpInst.addOperand(MCOperand::createReg(0)); in emitInstruction()
1502 TmpInst.addOperand(MCOperand::createReg(0)); in emitInstruction()
1805 TmpInst.addOperand(MCOperand::createReg(ARM::PC)); in emitInstruction()
1806 TmpInst.addOperand(MCOperand::createReg(MI->getOperand(0).getReg())); in emitInstruction()
1809 TmpInst.addOperand(MCOperand::createReg(0)); in emitInstruction()
[all …]
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/X86/Disassembler/
H A DX86Disassembler.cpp1777 mcInst.addOperand(MCOperand::createReg(llvmRegnum)); in translateRegister()
1845 MCOperand baseReg = MCOperand::createReg(baseRegNo); in translateSrcIndex()
1849 segmentReg = MCOperand::createReg(segmentRegnums[insn.segmentOverride]); in translateSrcIndex()
1870 MCOperand baseReg = MCOperand::createReg(baseRegNo); in translateDstIndex()
1956 mcInst.addOperand(MCOperand::createReg(X86::XMM0 + (immediate >> 4))); in translateImmediate()
1959 mcInst.addOperand(MCOperand::createReg(X86::YMM0 + (immediate >> 4))); in translateImmediate()
1962 mcInst.addOperand(MCOperand::createReg(X86::ZMM0 + (immediate >> 4))); in translateImmediate()
1976 segmentReg = MCOperand::createReg(segmentRegnums[insn.segmentOverride]); in translateImmediate()
2009 mcInst.addOperand(MCOperand::createReg(X86::x)); break; in translateRMRegister()
2056 baseReg = MCOperand::createReg(X86::x); break; in translateRMMemory()
[all …]
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARM/AsmParser/
H A DARMAsmParser.cpp2477 Inst.addOperand(MCOperand::createReg(RegNum)); in addCondCodeOperands()
2484 Inst.addOperand(MCOperand::createReg(RegNum)); in addVPTPredNOperands()
2501 Inst.addOperand(MCOperand::createReg(RegNum)); in addVPTPredROperands()
2536 Inst.addOperand(MCOperand::createReg(getReg())); in addCCOutOperands()
2541 Inst.addOperand(MCOperand::createReg(getReg())); in addRegOperands()
2548 Inst.addOperand(MCOperand::createReg(RegShiftedReg.SrcReg)); in addRegShiftedRegOperands()
2549 Inst.addOperand(MCOperand::createReg(RegShiftedReg.ShiftReg)); in addRegShiftedRegOperands()
2558 Inst.addOperand(MCOperand::createReg(RegShiftedImm.SrcReg)); in addRegShiftedImmOperands()
2576 Inst.addOperand(MCOperand::createReg(*I)); in addRegListOperands()
2584 Inst.addOperand(MCOperand::createReg(*I)); in addRegListWithAPSROperands()
[all …]
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/X86/AsmParser/
H A DX86Operand.h519 Inst.addOperand(MCOperand::createReg(getReg())); in addRegOperands()
527 Inst.addOperand(MCOperand::createReg(RegNo)); in addGR32orGR64Operands()
536 Inst.addOperand(MCOperand::createReg(RegNo)); in addGR16orGR32orGR64Operands()
570 Inst.addOperand(MCOperand::createReg(Reg)); in addMaskPairOperands()
576 Inst.addOperand(MCOperand::createReg(getMemBaseReg())); in addMemOperands()
578 Inst.addOperand(MCOperand::createReg(getMemDefaultBaseReg())); in addMemOperands()
580 Inst.addOperand(MCOperand::createReg(getMemIndexReg())); in addMemOperands()
582 Inst.addOperand(MCOperand::createReg(getMemSegReg())); in addMemOperands()
596 Inst.addOperand(MCOperand::createReg(getMemBaseReg())); in addSrcIdxOperands()
597 Inst.addOperand(MCOperand::createReg(getMemSegReg())); in addSrcIdxOperands()
[all …]
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
H A DAArch64AsmPrinter.cpp1037 CallTargetMCOp = MCOperand::createReg(CallTarget.getReg()); in LowerSTATEPOINT()
1077 MI.addOperand(MCOperand::createReg(DefRegister)); in LowerFAULTING_OP()
1104 MOVI.addOperand(MCOperand::createReg(DestReg)); in EmitFMov0()
1113 FMov.addOperand(MCOperand::createReg(DestReg)); in EmitFMov0()
1114 FMov.addOperand(MCOperand::createReg(AArch64::WZR)); in EmitFMov0()
1118 FMov.addOperand(MCOperand::createReg(DestReg)); in EmitFMov0()
1119 FMov.addOperand(MCOperand::createReg(AArch64::WZR)); in EmitFMov0()
1123 FMov.addOperand(MCOperand::createReg(DestReg)); in EmitFMov0()
1124 FMov.addOperand(MCOperand::createReg(AArch64::XZR)); in EmitFMov0()
1188 MovZ.addOperand(MCOperand::createReg(DestReg)); in emitInstruction()
[all …]
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/VE/
H A DVEAsmPrinter.cpp186 MCOperand MCRegOP = MCOperand::createReg(MO.getReg()); in lowerGETGOTAndEmitMCInsts()
203 MCOperand RegGOT = MCOperand::createReg(VE::SX15); // GOT in lowerGETGOTAndEmitMCInsts()
204 MCOperand RegPLT = MCOperand::createReg(VE::SX16); // PLT in lowerGETGOTAndEmitMCInsts()
225 MCOperand MCRegOP = MCOperand::createReg(MO.getReg()); in lowerGETFunPLTAndEmitMCInsts()
252 MCOperand RegPLT = MCOperand::createReg(VE::SX16); // PLT in lowerGETFunPLTAndEmitMCInsts()
293 MCOperand RegLR = MCOperand::createReg(VE::SX10); // LR in lowerGETTLSAddrAndEmitMCInsts()
294 MCOperand RegS0 = MCOperand::createReg(VE::SX0); // S0 in lowerGETTLSAddrAndEmitMCInsts()
295 MCOperand RegS12 = MCOperand::createReg(VE::SX12); // S12 in lowerGETTLSAddrAndEmitMCInsts()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Lanai/Disassembler/
H A DLanaiDisassembler.cpp170 Inst.addOperand(MCOperand::createReg(Reg)); in DecodeGPRRegisterClass()
179 Inst.addOperand(MCOperand::createReg(GPRDecoderTable[Register])); in decodeRiMemoryValue()
191 Inst.addOperand(MCOperand::createReg(GPRDecoderTable[Register])); in decodeRrMemoryValue()
193 Inst.addOperand(MCOperand::createReg(GPRDecoderTable[Register])); in decodeRrMemoryValue()
203 Inst.addOperand(MCOperand::createReg(GPRDecoderTable[Register])); in decodeSplsValue()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/
H A DRISCVMCInstLower.cpp100 MCOp = MCOperand::createReg(MO.getReg()); in LowerRISCVMachineOperandToMCOperand()
189 MCOp = MCOperand::createReg(Reg); in lowerRISCVVMachineInstrToMCInst()
202 OutMI.addOperand(MCOperand::createReg(RISCV::NoRegister)); in lowerRISCVVMachineInstrToMCInst()
238 OutMI.addOperand(MCOperand::createReg(RISCV::X0)); in lowerRISCVMachineInstrToMCInst()
244 OutMI.addOperand(MCOperand::createReg(RISCV::X0)); in lowerRISCVMachineInstrToMCInst()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Sparc/Disassembler/
H A DSparcDisassembler.cpp152 Inst.addOperand(MCOperand::createReg(Reg)); in DecodeIntRegsRegisterClass()
163 Inst.addOperand(MCOperand::createReg(Reg)); in DecodeI64RegsRegisterClass()
175 Inst.addOperand(MCOperand::createReg(Reg)); in DecodeFPRegsRegisterClass()
187 Inst.addOperand(MCOperand::createReg(Reg)); in DecodeDFPRegsRegisterClass()
202 Inst.addOperand(MCOperand::createReg(Reg)); in DecodeQFPRegsRegisterClass()
213 Inst.addOperand(MCOperand::createReg(Reg)); in DecodeCPRegsRegisterClass()
222 Inst.addOperand(MCOperand::createReg(FCCRegDecoderTable[RegNo])); in DecodeFCCRegsRegisterClass()
231 Inst.addOperand(MCOperand::createReg(ASRRegDecoderTable[RegNo])); in DecodeASRRegsRegisterClass()
240 Inst.addOperand(MCOperand::createReg(PRRegDecoderTable[RegNo])); in DecodePRRegsRegisterClass()
255 Inst.addOperand(MCOperand::createReg(RegisterPair)); in DecodeIntPairRegisterClass()
[all …]
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/BPF/Disassembler/
H A DBPFDisassembler.cpp107 Inst.addOperand(MCOperand::createReg(Reg)); in DecodeGPRRegisterClass()
122 Inst.addOperand(MCOperand::createReg(Reg)); in DecodeGPR32RegisterClass()
132 Inst.addOperand(MCOperand::createReg(GPRDecoderTable[Register])); in decodeMemoryOpValue()
213 Instr.addOperand(MCOperand::createReg(BPF::R6)); in getInstruction()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARM/Disassembler/
H A DARMDisassembler.cpp739 MI.insert(I, MCOperand::createReg(InITBlock ? 0 : ARM::CPSR)); in AddThumb1SBit()
744 MI.insert(I, MCOperand::createReg(InITBlock ? 0 : ARM::CPSR)); in AddThumb1SBit()
838 MI.insert(CCI, MCOperand::createReg(0)); in AddThumbPredicate()
840 MI.insert(CCI, MCOperand::createReg(ARM::CPSR)); in AddThumbPredicate()
855 MI.insert(VCCI, MCOperand::createReg(0)); in AddThumbPredicate()
857 MI.insert(VCCI, MCOperand::createReg(ARM::P0)); in AddThumbPredicate()
1139 Inst.addOperand(MCOperand::createReg(Register)); in DecodeGPRRegisterClass()
1153 Inst.addOperand(MCOperand::createReg(Register)); in DecodeCLRMGPRRegisterClass()
1177 Inst.addOperand(MCOperand::createReg(ARM::APSR_NZCV)); in DecodeGPRwithAPSRRegisterClass()
1192 Inst.addOperand(MCOperand::createReg(ARM::ZR)); in DecodeGPRwithZRRegisterClass()
[all …]
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/Disassembler/
H A DAArch64Disassembler.cpp336 Inst.addOperand(MCOperand::createReg(Register)); in DecodeFPR128RegisterClass()
365 Inst.addOperand(MCOperand::createReg(Register)); in DecodeFPR64RegisterClass()
386 Inst.addOperand(MCOperand::createReg(Register)); in DecodeFPR32RegisterClass()
407 Inst.addOperand(MCOperand::createReg(Register)); in DecodeFPR16RegisterClass()
428 Inst.addOperand(MCOperand::createReg(Register)); in DecodeFPR8RegisterClass()
449 Inst.addOperand(MCOperand::createReg(Register)); in DecodeGPR64commonRegisterClass()
460 Inst.addOperand(MCOperand::createReg(Register)); in DecodeGPR64RegisterClass()
489 Inst.addOperand(MCOperand::createReg(Register)); in DecodeGPR64x8ClassRegisterClass()
501 Inst.addOperand(MCOperand::createReg(Register)); in DecodeGPR64spRegisterClass()
522 Inst.addOperand(MCOperand::createReg(Register)); in DecodeGPR32RegisterClass()
[all …]
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/AsmParser/
H A DPPCAsmParser.cpp447 Inst.addOperand(MCOperand::createReg(RRegs[getReg()])); in addRegGPRCOperands()
452 Inst.addOperand(MCOperand::createReg(RRegsNoR0[getReg()])); in addRegGPRCNoR0Operands()
457 Inst.addOperand(MCOperand::createReg(XRegs[getReg()])); in addRegG8RCOperands()
462 Inst.addOperand(MCOperand::createReg(XRegsNoX0[getReg()])); in addRegG8RCNoX0Operands()
481 Inst.addOperand(MCOperand::createReg(FRegs[getReg()])); in addRegF4RCOperands()
486 Inst.addOperand(MCOperand::createReg(FRegs[getReg()])); in addRegF8RCOperands()
491 Inst.addOperand(MCOperand::createReg(VFRegs[getReg()])); in addRegVFRCOperands()
496 Inst.addOperand(MCOperand::createReg(VRegs[getReg()])); in addRegVRRCOperands()
501 Inst.addOperand(MCOperand::createReg(VSRegs[getVSReg()])); in addRegVSRCOperands()
506 Inst.addOperand(MCOperand::createReg(VSFRegs[getVSReg()])); in addRegVSFRCOperands()
[all …]
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/M68k/AsmParser/
H A DM68kAsmParser.cpp263 Inst.addOperand(MCOperand::createReg(getReg())); in addRegOperands()
317 Inst.addOperand(MCOperand::createReg(MemOp.OuterReg)); in addARIOperands()
327 Inst.addOperand(MCOperand::createReg(MemOp.OuterReg)); in addARIDOperands()
338 Inst.addOperand(MCOperand::createReg(MemOp.OuterReg)); in addARIIOperands()
339 Inst.addOperand(MCOperand::createReg(MemOp.InnerReg)); in addARIIOperands()
348 Inst.addOperand(MCOperand::createReg(MemOp.OuterReg)); in addARIPDOperands()
357 Inst.addOperand(MCOperand::createReg(MemOp.OuterReg)); in addARIPIOperands()
377 Inst.addOperand(MCOperand::createReg(MemOp.InnerReg)); in addPCIOperands()
/netbsd-src/external/apache2/llvm/dist/llvm/tools/llvm-exegesis/lib/
H A DParallelSnippetGenerator.cpp145 MCOperand::createReg(NextPossibleReg); in generateSnippetUsingStaticRenaming()
198 Variant.getValueFor(Op) = MCOperand::createReg(RandomReg); in generateCodeTemplates()
210 Variant.getValueFor(Op) = MCOperand::createReg(RandomReg); in generateCodeTemplates()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/MCTargetDesc/
H A DRISCVAsmBackend.cpp156 Res.addOperand(MCOperand::createReg(RISCV::X0)); in relaxInstruction()
163 Res.addOperand(MCOperand::createReg(RISCV::X0)); in relaxInstruction()
169 Res.addOperand(MCOperand::createReg(RISCV::X0)); in relaxInstruction()
175 Res.addOperand(MCOperand::createReg(RISCV::X1)); in relaxInstruction()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/SystemZ/AsmParser/
H A DSystemZAsmParser.cpp169 createReg(RegisterKind Kind, unsigned Num, SMLoc StartLoc, SMLoc EndLoc) { in createReg() function in __anond0f948490111::SystemZOperand
297 Inst.addOperand(MCOperand::createReg(getReg())); in addRegOperands()
306 Inst.addOperand(MCOperand::createReg(Mem.Base)); in addBDAddrOperands()
312 Inst.addOperand(MCOperand::createReg(Mem.Base)); in addBDXAddrOperands()
314 Inst.addOperand(MCOperand::createReg(Mem.Index)); in addBDXAddrOperands()
319 Inst.addOperand(MCOperand::createReg(Mem.Base)); in addBDLAddrOperands()
326 Inst.addOperand(MCOperand::createReg(Mem.Base)); in addBDRAddrOperands()
328 Inst.addOperand(MCOperand::createReg(Mem.Length.Reg)); in addBDRAddrOperands()
333 Inst.addOperand(MCOperand::createReg(Mem.Base)); in addBDVAddrOperands()
335 Inst.addOperand(MCOperand::createReg(Mem.Index)); in addBDVAddrOperands()
[all …]
/netbsd-src/external/apache2/llvm/dist/llvm/tools/llvm-exegesis/lib/PowerPC/
H A DTarget.cpp85 setMemOp(IT, DispOpIdx, MCOperand::createReg(PPC::X1)); in fillMemoryOperands()
88 setMemOp(IT, MemOpIdx + 2, MCOperand::createReg(Reg)); // BaseReg in fillMemoryOperands()

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