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Searched refs:cpsr (Results 1 – 25 of 77) sorted by relevance

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/netbsd-src/sys/external/bsd/compiler_rt/dist/test/builtins/Unit/arm/
H A Daeabi_cdcmple_test.c50 union cpsr cpsr = { .value = cpsr_value }; in test__aeabi_cdcmple() local
51 if (expected_z != cpsr.flags.z || expected_c != cpsr.flags.c) { in test__aeabi_cdcmple()
53 a, b, cpsr.flags.z, cpsr.flags.c, expected_z, expected_c); in test__aeabi_cdcmple()
57 cpsr.value = r_cpsr_value; in test__aeabi_cdcmple()
58 if (expected_z != cpsr.flags.z || expected_c != cpsr.flags.c) { in test__aeabi_cdcmple()
60 a, b, cpsr.flags.z, cpsr.flags.c, expected_z, expected_c); in test__aeabi_cdcmple()
H A Daeabi_cfcmple_test.c50 union cpsr cpsr = { .value = cpsr_value }; in test__aeabi_cfcmple() local
51 if (expected_z != cpsr.flags.z || expected_c != cpsr.flags.c) { in test__aeabi_cfcmple()
53 a, b, cpsr.flags.z, cpsr.flags.c, expected_z, expected_c); in test__aeabi_cfcmple()
57 cpsr.value = r_cpsr_value; in test__aeabi_cfcmple()
58 if (expected_z != cpsr.flags.z || expected_c != cpsr.flags.c) { in test__aeabi_cfcmple()
60 a, b, cpsr.flags.z, cpsr.flags.c, expected_z, expected_c); in test__aeabi_cfcmple()
H A Daeabi_cdcmpeq_test.c27 union cpsr cpsr = { .value = cpsr_value }; in test__aeabi_cdcmpeq() local
28 if (expected != cpsr.flags.z) { in test__aeabi_cdcmpeq()
30 a, b, cpsr.flags.z, expected); in test__aeabi_cdcmpeq()
H A Daeabi_cfcmpeq_test.c27 union cpsr cpsr = { .value = cpsr_value }; in test__aeabi_cfcmpeq() local
28 if (expected != cpsr.flags.z) { in test__aeabi_cfcmpeq()
30 a, b, cpsr.flags.z, expected); in test__aeabi_cfcmpeq()
/netbsd-src/sys/arch/arm/xscale/
H A Dpxa2x0_apm_asm.S170 msr cpsr, r1 /* Enter FIQ mode. */
175 msr cpsr, r1 /* Enter IRQ mode. */
180 msr cpsr, r1 /* Enter ABT mode. */
185 msr cpsr, r1 /* Enter UND mode. */
190 msr cpsr, r1 /* Enter SYS mode. */
194 msr cpsr, r1 /* Return to SVC mode. */
213 mrs r2, cpsr
220 mrs r2, cpsr
333 msr cpsr, r1
346 msr cpsr, r1
[all …]
/netbsd-src/sys/arch/hpc/stand/hpcboot/arm/
H A Darm.asm51 mrs r0, cpsr
54 msr cpsr, r0
59 mrs r0, cpsr
61 msr cpsr, r0
70 mrs r0, cpsr
72 msr cpsr, r0
77 mrs r0, cpsr
79 msr cpsr, r0
179 mrs r0, cpsr
185 msr cpsr, r0
/netbsd-src/sys/arch/arm/arm32/
H A Dspl.S64 mrs r4, cpsr
84 mrs r4, cpsr
107 mrs r4, cpsr
H A Dsetcpsr.S59 mrs r3, cpsr /* Set the CPSR */
76 mrs r0, cpsr /* Get the CPSR */
H A Dsetstack.S63 mrs r3, cpsr /* Switch to the appropriate mode */
83 mrs r3, cpsr /* Switch to the appropriate mode */
H A Dcpuswitch.S111 mrs r14, cpsr ; \
116 mrs r14, cpsr ; \
373 mrs r6, cpsr /* we need to save this */
/netbsd-src/sys/arch/arm/include/arm32/
H A Dframe.h143 mrs rb, cpsr /* fetch CPSR */
343 mrs r0, cpsr; /* Get the CPSR */ \
357 mrs rX, cpsr; /* Get the CPSR */ \
373 mrs r0, cpsr; /* Get the CPSR */ \
379 mrs r0, cpsr; /* Get the CPSR */ \
427 mrs tmp, cpsr; /* Get the CPSR */ \
/netbsd-src/sys/arch/arm/arm/
H A Dcpufunc_asm_sheeva.S43 mrs r4, cpsr
85 mrs r4, cpsr
127 mrs r4, cpsr
169 mrs r4, cpsr
218 mrs r4, cpsr
264 mrs r4, cpsr
308 mrs r4, cpsr
H A Dcpufunc_asm_arm11x6.S82 mrs Rtmp2, cpsr; \
149 mrs r2, cpsr /* save the CPSR */
181 mrs r2, cpsr /* save the CPSR */
/netbsd-src/external/gpl3/gdb/dist/sim/testsuite/arm/
H A Dmrs.cgs1 # arm testcase for mrs$cond $rd,cpsr
10 mrs0 pc,cpsr
H A Dmsr.cgs1 # arm testcase for msr$cond cpsr,$rm
10 msr0 cpsr,pc
H A Dtestutils.inc91 mrs r1, cpsr
94 msr cpsr, r1
113 mrs r1, cpsr
/netbsd-src/external/cddl/osnet/dev/dtrace/arm/
H A Ddtrace_asm.S66 mrs r0, cpsr
78 mrs r1, cpsr
218 mrs r3, cpsr
/netbsd-src/sys/arch/zaurus/stand/zbsdmod/
H A Dzbsdmod.c83 static int cpsr; variable
155 __asm volatile ("mrs %0, cpsr" : "=r" (cpsr)); in elf32bsdboot()
156 cpsr |= 0xc0; /* set FI */ in elf32bsdboot()
157 __asm volatile ("msr cpsr_all, %0" :: "r" (cpsr)); in elf32bsdboot()
/netbsd-src/external/gpl3/gdb/dist/sim/testsuite/arm/xscale/
H A Dtestutils.inc91 mrs r1, cpsr
94 msr cpsr, r1
113 mrs r1, cpsr
/netbsd-src/external/gpl3/gdb/dist/sim/testsuite/arm/iwmmxt/
H A Dtestutils.inc91 mrs r1, cpsr
94 msr cpsr, r1
113 mrs r1, cpsr
/netbsd-src/sys/arch/hpcarm/hpcarm/
H A Dlocore.S58 mrs r4, cpsr
196 mrs r2, cpsr
256 mrs r0, cpsr
/netbsd-src/sys/arch/arm/iomd/
H A Diomd_irqhandler.c380 u_int cpsr;
382 cpsr = SetCPSR(mask, mask);
383 return cpsr;
/netbsd-src/sys/arch/arm/sa11x0/
H A Dsa11x0_irq.S154 mrs r0, cpsr /* Enable IRQs */
234 mrs r0, cpsr
263 mrs r1, cpsr
/netbsd-src/sys/arch/shark/isa/
H A Disa_irq.S209 mrs r0, cpsr /* Enable IRQ's */
273 mrs r0, cpsr
303 mrs r3, cpsr
/netbsd-src/sys/arch/arm/ofw/
H A Dofw_irq.S252 mrs r0, cpsr /* Enable IRQ's */
320 mrs r0, cpsr
448 mrs r3, cpsr

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